📄 chandle.c
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*(p_uint32_t)(AITC_INTFRCH) &= ~0x04000000; // clear the bit in the force reg.
}
void norm_scr57_isr(void) // norm_scr57_isr (57)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x02000000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY7)>>4)&0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x02000000; // clear the bit in the force reg.
}
void norm_scr56_isr(void) // norm_scr56_isr (56)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x01000000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if((*(p_uint32_t)(AITC_NIPRIORITY7) & 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x01000000; // clear the bit in the force reg.
}
void norm_scr55_isr(void) // norm_scr55_isr (55)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00800000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY6)>>28)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00800000; // clear the bit in the force reg.
}
void norm_scr54_isr(void) // norm_scr54_isr (54)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00400000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY6)>>24)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00400000; // clear the bit in the force reg.
}
void norm_scr53_isr(void) // norm_scr53_isr (53)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00200000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY6)>>20)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00200000; // clear the bit in the force reg.
}
void norm_scr52_isr(void) // norm_scr52_isr (52)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00100000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY6)>>16)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00100000; // clear the bit in the force reg.
}
void norm_scr51_isr(void) // norm_scr51_isr (51)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00080000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY6)>>12)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00080000; // clear the bit in the force reg.
}
void norm_scr50_isr(void) // norm_scr50_isr (50)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00040000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY6)>>8)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00040000; // clear the bit in the force reg.
}
void norm_scr49_isr(void) // norm_scr49_isr (49)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00020000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY6)>>4)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00020000; // clear the bit in the force reg.
}
void norm_scr48_isr(void) // norm_scr48_isr (48)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00010000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY6))& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00010000; // clear the bit in the force reg.
}
void norm_scr47_isr(void) // norm_scr47_isr (47)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00008000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY5)>>28)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00008000; // clear the bit in the force reg.
}
void norm_scr46_isr(void) // norm_scr46_isr (46)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00004000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY5)>>24)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00004000; // clear the bit in the force reg.
}
void norm_scr45_isr(void) // norm_scr45_isr (45)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00002000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY5)>>20)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00002000; // clear the bit in the force reg.
}
void norm_scr44_isr(void) // norm_scr44_isr (44)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00001000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY5)>>16)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00001000;
}
void norm_scr43_isr(void) // norm_scr43_isr (43)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000800) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY5)>>12)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000800; // clear the bit in the force reg.
}
void norm_scr42_isr(void) // norm_scr42_isr (42)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000400) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY5)>>8)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000400; // clear the bit in the force reg.
}
void norm_scr41_isr(void) // norm_scr41_isr (41)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000200) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY5)>>4)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000200; // clear the bit in the force reg.
}
void norm_scr40_isr(void) // norm_scr40_isr (40)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000100) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY5))& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000100; // clear the bit in the force reg.
}
void norm_scr39_isr(void) // norm_scr39_isr (39)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000080) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY4)>>28)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000080; // clear the bit in the force reg.
}
void norm_scr38_isr(void) // norm_scr38_isr (38)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000040) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY4)>>24)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000040; // clear the bit in the force reg.
}
void norm_scr37_isr(void) // norm_scr37_isr (37)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000020) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY4)>>20)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000020; // clear the bit in the force reg.
}
void norm_scr36_isr(void) // norm_scr36_isr (36)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000010) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY4)>>16)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000010; // clear the bit in the force reg.
}
void norm_scr35_isr(void) // norm_scr35_isr (35)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000008) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY4)>>12)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000008; // clear the bit in the force reg.
}
void norm_scr34_isr(void) // norm_scr34_isr (34)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000004) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY4)>>8)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000004; // clear the bit in the force reg.
}
void norm_scr33_isr(void) // norm_scr33_isr (33)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000002) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY4)>>4)& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000002; // clear the bit in the force reg.
}
void norm_scr32_isr(void) // norm_scr32_isr (32)
{
if((*(p_uint32_t)(AITC_NIPNDH) & 0x00000001) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY4))& 0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCH) &= ~0x00000001; // clear the bit in the force reg.
gNormInt32flag = 1; // set flag
}
void norm_scr31_isr(void) // norm_scr31_isr (31)
{
if((*(p_uint32_t)(AITC_NIPNDL) & 0x80000000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY3)>>28)&0xF)!=(*(p_uint32_t)(AITC_NIVECSR)&0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCL) &= ~0x80000000; // clear the bit in the force reg.
}
void norm_scr30_isr(void) // norm_scr30_isr (30)
{
if((*(p_uint32_t)(AITC_NIPNDL) & 0x40000000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY3)>>24)&0xF)!=(*(p_uint32_t)(AITC_NIVECSR)&0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCL) &= ~0x40000000; // clear the bit in the force reg.
}
void norm_scr29_isr(void) // norm_scr29_isr (29)
{
if((*(p_uint32_t)(AITC_NIPNDL) & 0x20000000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
}
if(((*(p_uint32_t)(AITC_NIPRIORITY3)>>20)&0xF)!=(*(p_uint32_t)(AITC_NIVECSR)&0xF)) //verify interrupt priority
{
gFailPriorityCount++;
}
*(p_uint32_t)(AITC_INTFRCL) &= ~0x20000000; // clear the bit in the force reg.
}
void norm_scr28_isr(void) // norm_scr28_isr (28)
{
if((*(p_uint32_t)(AITC_NIPNDL) & 0x10000000) == 0) // verify the pending bit is set
{
gFailPendingCount++;
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