chandle.c

飞思卡尔imx27 wince5.0 bootloader源代码

    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00040000;		// clear the bit in the force reg.
}

void   fast_scr17_isr(void)	// fast_scr17_isr (17)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00020000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00020000;		// clear the bit in the force reg.
}

void   fast_scr49_isr(void)	// fast_scr49_isr (49)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00020000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00020000;		// clear the bit in the force reg.
}

void   fast_scr16_isr(void)	// fast_scr16_isr (16)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00010000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00010000;		// clear the bit in the force reg.
    gFastInt16flag = 1;
}

void   fast_scr48_isr(void)	// fast_scr48_isr (48)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00010000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00010000;		// clear the bit in the force reg.
}

void   fast_scr15_isr(void)	// fast_scr15_isr (15)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00008000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00008000;		// clear the bit in the force reg.
}

void   fast_scr47_isr(void)	// fast_scr47_isr (47)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00008000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00008000;		// clear the bit in the force reg.
}

void   fast_scr14_isr(void)	// fast_scr14_isr (14)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00004000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00004000;		// clear the bit in the force reg.
}

void   fast_scr46_isr(void)	// fast_scr46_isr (46)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00004000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00004000;		// clear the bit in the force reg.
}

void   fast_scr13_isr(void)	// fast_scr13_isr (13)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00002000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00002000;		// clear the bit in the force reg.
}

void   fast_scr45_isr(void)	// fast_scr45_isr (45)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00002000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00002000;		// clear the bit in the force reg.
}

void   fast_scr12_isr(void)	// fast_scr12_isr (12)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00001000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00001000;		// clear the bit in the force reg.
}

void   fast_scr44_isr(void)	// fast_scr44_isr (44)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00001000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00001000;		// clear the bit in the force reg.
}

void   fast_scr11_isr(void)	// fast_scr11_isr (11)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00000800) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00000800;		// clear the bit in the force reg.
}

void   fast_scr43_isr(void)	// fast_scr43_isr (43)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000800) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000800;		// clear the bit in the force reg.
}

void   fast_scr10_isr(void)	// fast_scr10_isr (10)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00000400) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00000400;		// clear the bit in the force reg.
}

void   fast_scr42_isr(void)	// fast_scr42_isr (42)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000400) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000400;		// clear the bit in the force reg.
}

void   fast_scr09_isr(void)	// fast_scr09_isr  (9)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00000200) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00000200;		// clear the bit in the force reg.
}

void   fast_scr41_isr(void)	// fast_scr41_isr (41)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000200) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000200;		// clear the bit in the force reg.
}

void   fast_scr08_isr(void)	// fast_scr08_isr  (8)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00000100) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00000100;		// clear the bit in the force reg.
    gFastInt8flag = 1;
}

void   fast_scr40_isr(void)	// fast_scr40_isr (40)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000100) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000100;		// clear the bit in the force reg.
}

void   fast_scr07_isr(void)	// fast_scr07_isr  (7)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x0000080) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x0000080;		// clear the bit in the force reg.
}

void   fast_scr39_isr(void)	// fast_scr39_isr (39)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000080) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000080;		// clear the bit in the force reg.
}

void   fast_scr06_isr(void)	// fast_scr06_isr  (6)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00000040) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00000040;		// clear the bit in the force reg.
}

void   fast_scr38_isr(void)	// fast_scr38_isr (38)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000040) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000040;		// clear the bit in the force reg.
}

void   fast_scr05_isr(void)	// fast_scr05_isr  (5)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00000020) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00000020;		// clear the bit in the force reg.
}

void   fast_scr37_isr(void)	// fast_scr37_isr (37)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000020) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000020;		// clear the bit in the force reg.
}

void   fast_scr04_isr(void)	// fast_scr04_isr  (4)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00000010) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00000010;		// clear the bit in the force reg.
    gFastInt4flag = 1;

}

void   fast_scr36_isr(void)	// fast_scr36_isr (36)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000010) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000010;		// clear the bit in the force reg.
}

void   fast_scr03_isr(void)	// fast_scr03_isr  (3)
{
	if((*(p_uint32_t)(AITC_FIPNDL) & 0x00000008) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00000008;		// clear the bit in the force reg.
}

void   fast_scr35_isr(void)	// fast_scr35_isr (35)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000008) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000008;		// clear the bit in the force reg.
}

void   fast_scr02_isr(void)	// fast_scr02_isr  (2)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00000004) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00000004;		// clear the bit in the force reg.
    gFastInt2flag = 1;
}

void   fast_scr34_isr(void)	// fast_scr34_isr (34)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000004) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000004;		// clear the bit in the force reg.
}

void   fast_scr01_isr(void)	// fast_scr01_isr  (1)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00000002) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00000002;		// clear the bit in the force reg.
    gFastInt1flag = 1;
}

void   fast_scr33_isr(void)	// fast_scr33_isr (33)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000002) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000002;		// clear the bit in the force reg.
}


void   fast_scr32_isr(void)	// fast_scr32_isr (32)
{
    if((*(p_uint32_t)(AITC_FIPNDH) & 0x00000001) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x00000001;		// clear the bit in the force reg.
    gFastInt32flag = 1;
}

void   fast_scr00_isr(void)	// fast_scr00_isr  (0)
{
    if((*(p_uint32_t)(AITC_FIPNDL) & 0x00000001) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

    *(p_uint32_t)(AITC_INTFRCL) &= ~0x00000001;		// clear the bit in the force reg.
    gFastInt0flag = 1;
}

/*************************/
/* Normal Interrupt ISRs */
/*************************/

void   norm_scr63_isr(void)	// norm_scr63_isr (63)
{
    if((*(p_uint32_t)(AITC_NIPNDH) & 0x80000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

	if(((*(p_uint32_t)(AITC_NIPRIORITY7)>>28)&0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x80000000;		// clear the bit in the force reg.
    gNormInt63flag = 1;

}

void   norm_scr62_isr(void)	// norm_scr62_isr (62)
{
    if((*(p_uint32_t)(AITC_NIPNDH) & 0x40000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

	if(((*(p_uint32_t)(AITC_NIPRIORITY7)>>24)&0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x40000000;		// clear the bit in the force reg.
    gNormInt62flag = 1;

}

void   norm_scr61_isr(void)	// norm_scr61_isr (61)
{
    if((*(p_uint32_t)(AITC_NIPNDH) & 0x20000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

	if(((*(p_uint32_t)(AITC_NIPRIORITY7)>>20)&0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x20000000;		// clear the bit in the force reg.
    gNormInt61flag = 1;

}

void   norm_scr60_isr(void)	// norm_scr60_isr (60)
{
    if((*(p_uint32_t)(AITC_NIPNDH) & 0x10000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

	if(((*(p_uint32_t)(AITC_NIPRIORITY7)>>16)&0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x10000000;		// clear the bit in the force reg.

}

void   norm_scr59_isr(void)	// norm_scr59_isr (59)
{
    if((*(p_uint32_t)(AITC_NIPNDH) & 0x08000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

	if(((*(p_uint32_t)(AITC_NIPRIORITY7)>>12)&0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}

    *(p_uint32_t)(AITC_INTFRCH) &= ~0x08000000;		// clear the bit in the force reg.
}

void   norm_scr58_isr(void)	// norm_scr58_isr (58)
{
    if((*(p_uint32_t)(AITC_NIPNDH) & 0x04000000) == 0)	// verify the pending bit is set
    {
    	gFailPendingCount++;
    }

	if(((*(p_uint32_t)(AITC_NIPRIORITY7)>>8)&0xF)!=(*(p_uint32_t)(AITC_NIVECSR) & 0xF)) //verify interrupt priority
	{
		gFailPriorityCount++;
	}