bono_memory_map_defines.h

飞思卡尔imx27 wince5.0 bootloader源代码

#define DMA_DISR                 (DMA_SYS_BASE+0x004)       // 32bit dma interrupt status reg
#define DMA_DIMR                 (DMA_SYS_BASE+0x008)       // 32bit dma interrupt mask reg
#define DMA_DBTOSR               (DMA_SYS_BASE+0x00C)       // 32bit dma burst timeout stat reg
#define DMA_DRTOSR               (DMA_SYS_BASE+0x010)       // 32bit dma req timeout status reg
#define DMA_DSESR                (DMA_SYS_BASE+0x014)       // 32bit dma transfer err status reg
#define DMA_DBOSR                (DMA_SYS_BASE+0x018)       // 32bit dma buffer overflow stat reg
#define DMA_DBTOCR               (DMA_SYS_BASE+0x01C)       // 32bit dma burst timeout ctrl reg

#define DMA_WSRA                 (DMA_M2D_BASE+0x000)       // 32bit dma W-size A reg
#define DMA_XSRA                 (DMA_M2D_BASE+0x004)       // 32bit dma X-size A reg
#define DMA_YSRA                 (DMA_M2D_BASE+0x008)       // 32bit dma Y-size A reg
#define DMA_WSRB                 (DMA_M2D_BASE+0x00C)       // 32bit dma W-size B reg
#define DMA_XSRB                 (DMA_M2D_BASE+0x010)       // 32bit dma X-size B reg
#define DMA_YSRB                 (DMA_M2D_BASE+0x014)       // 32bit dma Y-size B reg

#define DMA_SAR0                 (DMA_CH0_BASE+0x000)       // 32bit dma ch0 source addr reg
#define DMA_DAR0                 (DMA_CH0_BASE+0x004)       // 32bit dma ch0 dest addr reg
#define DMA_CNTR0                (DMA_CH0_BASE+0x008)       // 32bit dma ch0 count reg
#define DMA_CCR0                 (DMA_CH0_BASE+0x00C)       // 32bit dma ch0 control reg
#define DMA_RSSR0                (DMA_CH0_BASE+0x010)       // 32bit dma ch0 req source sel reg
#define DMA_BLR0                 (DMA_CH0_BASE+0x014)       // 32bit dma ch0 burst lenght reg
#define DMA_RTOR0                (DMA_CH0_BASE+0x018)       // 32bit dma ch0 req time out reg
#define DMA_BUCR0                (DMA_CH0_BASE+0x018)       // 32bit dma ch0 bus utilization reg
#define DMA_CCNR0                (DMA_CH0_BASE+0x01C)       // 32bit dma ch0 counter reg

#define DMA_SAR1                 (DMA_CH1_BASE+0x000)       // 32bit dma ch1 source addr reg
#define DMA_DAR1                 (DMA_CH1_BASE+0x004)       // 32bit dma ch1 dest addr reg
#define DMA_CNTR1                (DMA_CH1_BASE+0x008)       // 32bit dma ch1 count reg
#define DMA_CCR1                 (DMA_CH1_BASE+0x00C)       // 32bit dma ch1 control reg
#define DMA_RSSR1                (DMA_CH1_BASE+0x010)       // 32bit dma ch1 req source sel reg
#define DMA_BLR1                 (DMA_CH1_BASE+0x014)       // 32bit dma ch1 burst lenght reg
#define DMA_RTOR1                (DMA_CH1_BASE+0x018)       // 32bit dma ch1 req time out reg
#define DMA_BUCR1                (DMA_CH1_BASE+0x018)       // 32bit dma ch1 bus utilization reg
#define DMA_CCNR1                (DMA_CH1_BASE+0x01C)       // 32bit dma ch1 counter reg

#define DMA_SAR2                 (DMA_CH2_BASE+0x000)       // 32bit dma ch2 source addr reg
#define DMA_DAR2                 (DMA_CH2_BASE+0x004)       // 32bit dma ch2 dest addr reg
#define DMA_CNTR2                (DMA_CH2_BASE+0x008)       // 32bit dma ch2 count reg
#define DMA_CCR2                 (DMA_CH2_BASE+0x00C)       // 32bit dma ch2 control reg
#define DMA_RSSR2                (DMA_CH2_BASE+0x010)       // 32bit dma ch2 req source sel reg
#define DMA_BLR2                 (DMA_CH2_BASE+0x014)       // 32bit dma ch2 burst lenght reg
#define DMA_RTOR2                (DMA_CH2_BASE+0x018)       // 32bit dma ch2 req time out reg
#define DMA_BUCR2                (DMA_CH2_BASE+0x018)       // 32bit dma ch2 bus utilization reg
#define DMA_CCNR2                (DMA_CH2_BASE+0x01C)       // 32bit dma ch2 counter reg

#define DMA_SAR3                 (DMA_CH3_BASE+0x000)       // 32bit dma ch3 source addr reg
#define DMA_DAR3                 (DMA_CH3_BASE+0x004)       // 32bit dma ch3 dest addr reg
#define DMA_CNTR3                (DMA_CH3_BASE+0x008)       // 32bit dma ch3 count reg
#define DMA_CCR3                 (DMA_CH3_BASE+0x00C)       // 32bit dma ch3 control reg
#define DMA_RSSR3                (DMA_CH3_BASE+0x010)       // 32bit dma ch3 req source sel reg
#define DMA_BLR3                 (DMA_CH3_BASE+0x014)       // 32bit dma ch3 burst lenght reg
#define DMA_RTOR3                (DMA_CH3_BASE+0x018)       // 32bit dma ch3 req time out reg
#define DMA_BUCR3                (DMA_CH3_BASE+0x018)       // 32bit dma ch3 bus utilization reg
#define DMA_CCNR3                (DMA_CH3_BASE+0x01C)       // 32bit dma ch3 counter reg

#define DMA_SAR4                 (DMA_CH4_BASE+0x000)       // 32bit dma ch4 source addr reg
#define DMA_DAR4                 (DMA_CH4_BASE+0x004)       // 32bit dma ch4 dest addr reg
#define DMA_CNTR4                (DMA_CH4_BASE+0x008)       // 32bit dma ch4 count reg
#define DMA_CCR4                 (DMA_CH4_BASE+0x00C)       // 32bit dma ch4 control reg
#define DMA_RSSR4                (DMA_CH4_BASE+0x010)       // 32bit dma ch4 req source sel reg
#define DMA_BLR4                 (DMA_CH4_BASE+0x014)       // 32bit dma ch4 burst lenght reg
#define DMA_RTOR4                (DMA_CH4_BASE+0x018)       // 32bit dma ch4 req time out reg
#define DMA_BUCR4                (DMA_CH4_BASE+0x018)       // 32bit dma ch4 bus utilization reg
#define DMA_CCNR4                (DMA_CH4_BASE+0x01C)       // 32bit dma ch4 counter reg

#define DMA_SAR5                 (DMA_CH5_BASE+0x000)       // 32bit dma ch5 source addr reg
#define DMA_DAR5                 (DMA_CH5_BASE+0x004)       // 32bit dma ch5 dest addr reg
#define DMA_CNTR5                (DMA_CH5_BASE+0x008)       // 32bit dma ch5 count reg
#define DMA_CCR5                 (DMA_CH5_BASE+0x00C)       // 32bit dma ch5 control reg
#define DMA_RSSR5                (DMA_CH5_BASE+0x010)       // 32bit dma ch5 req source sel reg
#define DMA_BLR5                 (DMA_CH5_BASE+0x014)       // 32bit dma ch5 burst lenght reg
#define DMA_RTOR5                (DMA_CH5_BASE+0x018)       // 32bit dma ch5 req time out reg
#define DMA_BUCR5                (DMA_CH5_BASE+0x018)       // 32bit dma ch5 bus utilization reg
#define DMA_CCNR5                (DMA_CH5_BASE+0x01C)       // 32bit dma ch5 counter reg

#define DMA_SAR6                 (DMA_CH6_BASE+0x000)       // 32bit dma ch6 source addr reg
#define DMA_DAR6                 (DMA_CH6_BASE+0x004)       // 32bit dma ch6 dest addr reg
#define DMA_CNTR6                (DMA_CH6_BASE+0x008)       // 32bit dma ch6 count reg
#define DMA_CCR6                 (DMA_CH6_BASE+0x00C)       // 32bit dma ch6 control reg
#define DMA_RSSR6                (DMA_CH6_BASE+0x010)       // 32bit dma ch6 req source sel reg
#define DMA_BLR6                 (DMA_CH6_BASE+0x014)       // 32bit dma ch6 burst lenght reg
#define DMA_RTOR6                (DMA_CH6_BASE+0x018)       // 32bit dma ch6 req time out reg
#define DMA_BUCR6                (DMA_CH6_BASE+0x018)       // 32bit dma ch6 bus utilization reg
#define DMA_CCNR6                (DMA_CH6_BASE+0x01C)       // 32bit dma ch6 counter reg

#define DMA_SAR7                 (DMA_CH7_BASE+0x000)       // 32bit dma ch7 source addr reg
#define DMA_DAR7                 (DMA_CH7_BASE+0x004)       // 32bit dma ch7 dest addr reg
#define DMA_CNTR7                (DMA_CH7_BASE+0x008)       // 32bit dma ch7 count reg
#define DMA_CCR7                 (DMA_CH7_BASE+0x00C)       // 32bit dma ch7 control reg
#define DMA_RSSR7                (DMA_CH7_BASE+0x010)       // 32bit dma ch7 req source sel reg
#define DMA_BLR7                 (DMA_CH7_BASE+0x014)       // 32bit dma ch7 burst lenght reg
#define DMA_RTOR7                (DMA_CH7_BASE+0x018)       // 32bit dma ch7 req time out reg
#define DMA_BUCR7                (DMA_CH7_BASE+0x018)       // 32bit dma ch7 bus utilization reg
#define DMA_CCNR7                (DMA_CH7_BASE+0x01C)       // 32bit dma ch7 counter reg

#define DMA_SAR8                 (DMA_CH8_BASE+0x000)       // 32bit dma ch8 source addr reg
#define DMA_DAR8                 (DMA_CH8_BASE+0x004)       // 32bit dma ch8 dest addr reg
#define DMA_CNTR8                (DMA_CH8_BASE+0x008)       // 32bit dma ch8 count reg
#define DMA_CCR8                 (DMA_CH8_BASE+0x00C)       // 32bit dma ch8 control reg
#define DMA_RSSR8                (DMA_CH8_BASE+0x010)       // 32bit dma ch8 req source sel reg
#define DMA_BLR8                 (DMA_CH8_BASE+0x014)       // 32bit dma ch8 burst lenght reg
#define DMA_RTOR8                (DMA_CH8_BASE+0x018)       // 32bit dma ch8 req time out reg
#define DMA_BUCR8                (DMA_CH8_BASE+0x018)       // 32bit dma ch8 bus utilization reg
#define DMA_CCNR8                (DMA_CH8_BASE+0x01C)       // 32bit dma ch8 counter reg

#define DMA_SAR9                 (DMA_CH9_BASE+0x000)       // 32bit dma ch9 source addr reg
#define DMA_DAR9                 (DMA_CH9_BASE+0x004)       // 32bit dma ch9 dest addr reg
#define DMA_CNTR9                (DMA_CH9_BASE+0x008)       // 32bit dma ch9 count reg
#define DMA_CCR9                 (DMA_CH9_BASE+0x00C)       // 32bit dma ch9 control reg
#define DMA_RSSR9                (DMA_CH9_BASE+0x010)       // 32bit dma ch9 req source sel reg
#define DMA_BLR9                 (DMA_CH9_BASE+0x014)       // 32bit dma ch9 burst lenght reg
#define DMA_RTOR9                (DMA_CH9_BASE+0x018)       // 32bit dma ch9 req time out reg
#define DMA_BUCR9                (DMA_CH9_BASE+0x018)       // 32bit dma ch9 bus utilization reg
#define DMA_CCNR9                (DMA_CH9_BASE+0x01C)       // 32bit dma ch9 counter reg

#define DMA_SAR10                (DMA_CH10_BASE+0x000)      // 32bit dma ch10 source addr reg
#define DMA_DAR10                (DMA_CH10_BASE+0x004)      // 32bit dma ch10 dest addr reg
#define DMA_CNTR10               (DMA_CH10_BASE+0x008)      // 32bit dma ch10 count reg
#define DMA_CCR10                (DMA_CH10_BASE+0x00C)      // 32bit dma ch10 control reg
#define DMA_RSSR10               (DMA_CH10_BASE+0x010)      // 32bit dma ch10 req source sel reg
#define DMA_BLR10                (DMA_CH10_BASE+0x014)      // 32bit dma ch10 burst lenght reg
#define DMA_RTOR10               (DMA_CH10_BASE+0x018)      // 32bit dma ch10 req time out reg
#define DMA_BUCR10               (DMA_CH10_BASE+0x018)      // 32bit dma ch10 bus utilization reg
#define DMA_CCNR10               (DMA_CH10_BASE+0x01C)      // 32bit dma ch10 counter reg

#define DMA_SAR11                (DMA_CH11_BASE+0x000)      // 32bit dma ch11 source addr reg
#define DMA_DAR11                (DMA_CH11_BASE+0x004)      // 32bit dma ch11 dest addr reg
#define DMA_CNTR11               (DMA_CH11_BASE+0x008)      // 32bit dma ch11 count reg
#define DMA_CCR11                (DMA_CH11_BASE+0x00C)      // 32bit dma ch11 control reg
#define DMA_RSSR11               (DMA_CH11_BASE+0x010)      // 32bit dma ch11 req source sel reg
#define DMA_BLR11                (DMA_CH11_BASE+0x014)      // 32bit dma ch11 burst lenght reg
#define DMA_RTOR11               (DMA_CH11_BASE+0x018)      // 32bit dma ch11 req time out reg
#define DMA_BUCR11               (DMA_CH11_BASE+0x018)      // 32bit dma ch11 bus utilization reg
#define DMA_CCNR11               (DMA_CH11_BASE+0x01C)      // 32bit dma ch11 counter reg

#define DMA_SAR12                (DMA_CH12_BASE+0x000)      // 32bit dma ch12 source addr reg
#define DMA_DAR12                (DMA_CH12_BASE+0x004)      // 32bit dma ch12 dest addr reg
#define DMA_CNTR12               (DMA_CH12_BASE+0x008)      // 32bit dma ch12 count reg
#define DMA_CCR12                (DMA_CH12_BASE+0x00C)      // 32bit dma ch12 control reg
#define DMA_RSSR12               (DMA_CH12_BASE+0x010)      // 32bit dma ch12 req source sel reg
#define DMA_BLR12                (DMA_CH12_BASE+0x014)      // 32bit dma ch12 burst lenght reg
#define DMA_RTOR12               (DMA_CH12_BASE+0x018)      // 32bit dma ch12 req time out reg
#define DMA_BUCR12               (DMA_CH12_BASE+0x018)      // 32bit dma ch12 bus utilization reg
#define DMA_CCNR12               (DMA_CH12_BASE+0x01C)      // 32bit dma ch12 counter reg

#define DMA_SAR13                (DMA_CH13_BASE+0x000)      // 32bit dma ch13 source addr reg
#define DMA_DAR13                (DMA_CH13_BASE+0x004)      // 32bit dma ch13 dest addr reg
#define DMA_CNTR13               (DMA_CH13_BASE+0x008)      // 32bit dma ch13 count reg
#define DMA_CCR13                (DMA_CH13_BASE+0x00C)      // 32bit dma ch13 control reg
#define DMA_RSSR13               (DMA_CH13_BASE+0x010)      // 32bit dma ch13 req source sel reg
#define DMA_BLR13                (DMA_CH13_BASE+0x014)      // 32bit dma ch13 burst lenght reg
#define DMA_RTOR13               (DMA_CH13_BASE+0x018)      // 32bit dma ch13 req time out reg
#define DMA_BUCR13               (DMA_CH13_BASE+0x018)      // 32bit dma ch13 bus utilization reg
#define DMA_CCNR13               (DMA_CH13_BASE+0x01C)      // 32bit dma ch13 counter reg

#define DMA_SAR14                (DMA_CH14_BASE+0x000)      // 32bit dma ch14 source addr reg
#define DMA_DAR14                (DMA_CH14_BASE+0x004)      // 32bit dma ch14 dest addr reg
#define DMA_CNTR14               (DMA_CH14_BASE+0x008)      // 32bit dma ch14 count reg
#define DMA_CCR14                (DMA_CH14_BASE+0x00C)      // 32bit dma ch14 control reg
#define DMA_RSSR14               (DMA_CH14_BASE+0x010)      // 32bit dma ch14 req source sel reg
#define DMA_BLR14                (DMA_CH14_BASE+0x014)      // 32bit dma ch14 burst lenght reg
#define DMA_RTOR14               (DMA_CH14_BASE+0x018)      // 32bit dma ch14 req time out reg
#define DMA_BUCR14               (DMA_CH14_BASE+0x018)      // 32bit dma ch14 bus utilization reg
#define DMA_CCNR14               (DMA_CH14_BASE+0x01C)      // 32bit dma ch14 counter reg

#define DMA_SAR15                (DMA_CH15_BASE+0x000)      // 32bit dma ch15 source addr reg
#define DMA_DAR15                (DMA_CH15_BASE+0x004)      // 32bit dma ch15 dest addr reg
#define DMA_CNTR15               (DMA_CH15_BASE+0x008)      // 32bit dma ch15 count reg
#define DMA_CCR15                (DMA_CH15_BASE+0x00C)      // 32bit dma ch15 control reg
#define DMA_RSSR15               (DMA_CH15_BASE+0x010)      // 32bit dma ch15 req source sel reg
#define DMA_BLR15                (DMA_CH15_BASE+0x014)      // 32bit dma ch15 burst lenght reg
#define DMA_RTOR15               (DMA_CH15_BASE+0x018)      // 32bit dma ch15 req time out reg
#define DMA_BUCR15               (DMA_CH15_BASE+0x018)      // 32bit dma ch15 bus utilization reg
#define DMA_CCNR15               (DMA_CH15_BASE+0x01C)      // 32bit dma ch15 counter reg

#define DMA_TCR                  (DMA_TEST_BASE+0x000)      // 32bit dma test control reg
#define DMA_TFIFOAR              (DMA_TEST_BASE+0x004)      // 32bit dma test fifo A reg
#define DMA_TDIPR                (DMA_TEST_BASE+0x00C)      // 32bit dma test in progress reg
#define DMA_TFIFOBR              (DMA_TEST_BASE+0x010)      // 32bit dma test fifo B reg
#define DMA_TDRR_L               (DMA_TEST_BASE+0x018)      // 64bit dma test request reg low 32bit
#define DMA_TDRR_H               (DMA_TEST_BASE+0x01C)      // 64bit dma test request reg high 32bit

// #########################################
// # WDOG                                  #
// # $1000_2000 to $1000_2FFF              #