📄 startup.s
字号:
;
; Enable ICache (TODO: Could we turn on it here??)
;
; mrc p15, 0, r0, c1, c0, 0 ; r0 = system control reg
; orr r0, r0, #ARM_CTRL_ICACHE ; enable ICache
; mcr p15, 0, r0, c1, c0, 0 ; update system control reg
; CPWAIT ; wait cp15 ready
;
; Set up temporary stack to VRAM (45KB on MX27: 0xFFFF4C00 - 0xFFFFFFFF)
; (TODO: Is it need? If no more params to pass.)
;
ldr sp, =0xFFFFFFFC
;
; Call OEM-specific system control initialization
;
bl OALSetUpSystemControl
;
; Call OEM-specific clock initialization
;
bl OALSetUpFrequencies
;
; Call OEM-specific GPIO initialization
;
bl OALSetUpGpio
;
; Initialize Wireless External Interface Module (WEIM)
;
bl WeimInit
;
; Only configure ESDRAMC if running from SDRAM
;
ldr r1, =CSP_BASE_MEM_PA_CS0
cmp pc, r1
blt skip_esdramc_init
bl EsdramcInit
skip_esdramc_init
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Flush or invalidate the instruction and data caches and the translation
; look-aside buffer (TLB) and empty the write buffers
;--------------------------------------------------------------------------
; TODO: Need on MX27??
; bl OALClearUTLB
; mov r0, #0
; mcr p15, 0, r0, c7, c7, 0 ; flush the unified cache
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Configure the interrupt controller. Mask and clear any pending
; interrupts.
;--------------------------------------------------------------------------
mov r0, #0
ldr r1, =CSP_BASE_REG_PA_AITC
str r0, [r1, #AITC_INTENABLEH_OFFSET] ; disable all interrupt sources
str r0, [r1, #AITC_INTENABLEL_OFFSET]
str r0, [r1, #AITC_INTTYPEH_OFFSET] ; all sources generate normal IRQ
str r0, [r1, #AITC_INTTYPEL_OFFSET]
str r0, [r1, #AITC_INTFRCH_OFFSET] ; no sources forced
str r0, [r1, #AITC_INTFRCL_OFFSET]
str r0, [r1, #AITC_NIPRIORITY7_OFFSET] ; all sources lowest priority
str r0, [r1, #AITC_NIPRIORITY6_OFFSET]
str r0, [r1, #AITC_NIPRIORITY5_OFFSET]
str r0, [r1, #AITC_NIPRIORITY4_OFFSET]
str r0, [r1, #AITC_NIPRIORITY3_OFFSET]
str r0, [r1, #AITC_NIPRIORITY2_OFFSET]
str r0, [r1, #AITC_NIPRIORITY1_OFFSET]
str r0, [r1, #AITC_NIPRIORITY0_OFFSET]
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Get the physical base address of the OEMAddressTable and store in r0.
;--------------------------------------------------------------------------
adr r0, g_oalAddressTable
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Jump to KernelStart to boot WindowsCE or BootloaderMain for bootloader
;--------------------------------------------------------------------------
b KernelStart
spin
b spin
;
; Include memory configuration file with g_oalAddressTable
;
INCLUDE oemaddrtab_cfg.inc
ENTRY_END StartUp
LTORG ; insert a literal pool here.
;------------------------------------------------------------------------------
;
; Function: WeimInit
;
; This function initializes Wireless External Interface Module (WEIM).
; Phyiscal address is used only.
;
; Parameters:
; None.
;
; Retruns:
; None.
;
;------------------------------------------------------------------------------
LEAF_ENTRY WeimInit
;
; Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
;
ldr r1, =CSP_BASE_MEM_PA_CS0
ldr r0, =0xF0F0
strh r0, [r1]
; 1st command
ldr r2, =0xAAA
add r2, r2, r1
ldr r0, =0xAAAA
strh r0, [r2]
; 2nd command
ldr r2, =0x554
add r2, r2, r1
ldr r0, =0x5555
strh r0, [r2]
; 3rd command
ldr r2, =0xAAA
add r2, r2, r1
ldr r0, =0xD0D0
strh r0, [r2]
; Write flash config register
ldr r0, =0x56CA
strh r0, [r2]
; Flash reset command
ldr r0, =0xF0F0
strh r0, [r1]
;
; Configure WEIM registers
;
ldr r1, =CSP_BASE_REG_PA_WEIM
; CS0 control (upper)
; EDC - 3 extra dead cycles (3 << 0) = 0x00000003
; WWS - 0 extra write wait states (0 << 4) = 0x00000000
; EW - Posedge DTACK (0 << 7) = 0x00000000
; WSC - 12 wait states (12 << 8) = 0x00000C00
; CNC - 3 CS negation cycles (3 << 14) = 0x0000C000
; DOL - 0 clock burst latency (0 << 16) = 0x00000000
; SYNC - Disable sync burst (0 << 20) = 0x00000000
; PME - Disable page mode (0 << 21) = 0x00000000
; PSZ - 4 word burst/page (0 << 22) = 0x00000000
; BCS - 1 BCLK delay (0 << 24) = 0x00000000
; BCD - /1 burst clock (0 << 28) = 0x00000000
; WP - No write protect (0 << 30) = 0x00000000
; SP - All user mode access (0 << 31) = 0x00000000
; ------------
; 0x0000CC03
;ldr r0, =0x0000CC03
ldr r0, =0x23524E80
str r0, [r1, #WEIM_CSCR0U_OFFSET]
; CS0 control (lower)
; CSEN - Enable chip select (1 << 0) = 0x00000001
; WRAP - No wrap (0 << 1) = 0x00000000
; CRE - CRE pin 0 (0 << 2) = 0x00000000
; PSR - PSRAM mode disabled (0 << 3) = 0x00000000
; CSN - 2 AHB clocks (2 << 4) = 0x00000000
; DSZ - 16-bit DATA[15:0] (5 << 8) = 0x00000500
; EBC - Only write asserts EB (1 << 11) = 0x00000800
; CSA - 2 half AHB clocks (0 << 12) = 0x00000000
; EBWN - 3 half AHB clocks (3 << 16) = 0x00030000
; EBWA - 3 half AHB clocks (3 << 20) = 0x00300000
; OEN - 2 half AHB clocks (0 << 24) = 0x00000000
; OEA - 10 half AHB clocks (10 << 28) = 0xA0000000
; ------------
; 0xA0330D01
;ldr r0, =0xA0330D01
ldr r0, =0x10000D03
str r0, [r1, #WEIM_CSCR0L_OFFSET]
; CS0 control (additional)
; FCE - Data capture by AHB clk (0 << 0) = 0x00000000
; CNC2 - No CNC increase (0 << 1) = 0x00000000
; AGE - Disable ack glue logic (0 << 2) = 0x00000000
; WWU - Forbit wrap on write (0 << 3) = 0x00000000
; DCT - 2 AHB clocks (0 << 4) = 0x00000000
; DWW - wait states same as read (0 << 6) = 0x00000000
; LBA - 0 half AHB clock (0 << 8) = 0x00000000
; LBN - 2 half AHB clocks (2 << 10) = 0x00000800
; LAH - 3 half AHB clocks (2 << 13) = 0x00000000
; MUM - Non-muxed mode (0 << 14) = 0x00000000
; RWN - 2 half AHB clocks (2 << 16) = 0x00020000
; RWA - 2 half AHB clocks (2 << 20) = 0x00200000
; EBRN - 0 half AHB clocks (0 << 24) = 0x00000000
; EBRA - 0 half AHB clocks (0 << 28) = 0x00000000
; ------------
; 0x00220800
;ldr r0, =0x00220800
ldr r0, =0x00720900
str r0, [r1, #WEIM_CSCR0A_OFFSET]
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return to caller.
ENDIF
ENTRY_END WeimInit
LTORG ; insert a literal pool here.
;------------------------------------------------------------------------------
;
; Function: EsdramcInit
;
; This function initializes Enhanced SDRAM Controller. Phyiscal address is
; used only.
;
; Parameters:
; None.
;
; Retruns:
; None.
;
;------------------------------------------------------------------------------
LEAF_ENTRY EsdramcInit
;
; Configure enhanced SDRAM/DDR contoller (ESDRAMC)
;
ldr r1, =CSP_BASE_REG_PA_ESDRAMC
ldr r2, =CSP_BASE_MEM_PA_CSD0
; Configure SDRAM timing parameters
ldr r0, =0x006AC73A
str r0, [r1, #ESDRAMC_ESDCFG0_OFFSET]
; Reset
ldr r0, =0x2
str r0, [r1, #ESDRAMC_ESDMISC_OFFSET]
; Configure for DDR
ldr r0, =0x4
str r0, [r1, #ESDRAMC_ESDMISC_OFFSET]
; Hold for more than 200us
ldr r0, =0x10000
hold
subs r0, r0, #0x1
bne hold
; Set precharge command
;
; COL - 9 column addresses (1 << 20) = 0x00100000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Precharge command (1 << 28) = 0x10000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0x92100000
ldr r0, =0x92100000
str r0, [r1, #ESDRAMC_ESDCTL0_OFFSET]
; Access SDRAM with A10 high to precharge all banks
ldr r0, =0x0
str r0, [r2, #0xF00]
; Set autorefresh command
;
; COL - 9 column addresses (1 << 20) = 0x00100000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Autorefresh command (2 << 28) = 0x20000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0xA2100000
ldr r0, =0xA2100000
str r0, [r1, #ESDRAMC_ESDCTL0_OFFSET]
; Use writes to refresh all banks of SDRAM
ldr r0, =0x0
str r0, [r2]
str r0, [r2]
; Set load mode command
;
; COL - 9 column addresses (1 << 20) = 0x00100000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Load mode command (3 << 28) = 0x30000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0xB2100000
ldr r0, =0xB2100000
str r0, [r1, #ESDRAMC_ESDCTL0_OFFSET]
; Use SDRAM write to load SDRAM mode register
ldr r0, =0x0
strb r0, [r2, #0x33] ; address used for mode, data ignored
ldr r3, =(CSP_BASE_MEM_PA_CSD0 + 0x01000000)
strb r0, [r3] ; address used for mode, data ignored
; Set normal mode command
;
; PRCT - Precharge timer disabled (0 << 0) = 0x00000000
; BL - Burst of 8 for SDR/DDR (1 << 7) = 0x00000080
; FP - No full page mode (0 << 8) = 0x00000000
; PWDT - Power down timeout 128 clocks (3 << 10) = 0x00000C00
; SREFR - 4 rows refreshed each clock (3 << 13) = 0x00006000
; DSIZ - 32-bit memory width (2 << 16) = 0x00020000
; COL - 10 column addresses (2 << 20) = 0x00200000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Normal mode command (0 << 28) = 0x00000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0x82226C80
ldr r0, =0x82226C80
str r0, [r1, #ESDRAMC_ESDCTL0_OFFSET]
; Configure misc SDRAM parameters
ldr r0, =0xC
str r0, [r1, #ESDRAMC_ESDMISC_OFFSET]
; Increase hold time on DDR write delay lines
; ldr r0, =0x60000
; str r0, [r1, #ESDRAMC_ESDDLY5_OFFSET]
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return to caller.
ENDIF
ENTRY_END EsdramcInit
LTORG ; insert a literal pool here.
END
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -