📄 startup.s
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;------------------------------------------------------------------------------
;
; Copyright (C) 2006, Freescale Semiconductor, Inc. All Rights Reserved
; THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
; BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
; FREESCALE SEMICONDUCTOR, INC.
;
;------------------------------------------------------------------------------
;
; File: startup.s
;
; This file implements MX27 common initialization code. It's responsible
; for setting up the MX27 core before jumping to OEM-specific codes for
; board-level initialization.
;
;------------------------------------------------------------------------------
OPT 2 ; Disable listing
INCLUDE kxarm.h ; This defines the WinCE/ARM Calling Sequence
; Specification
INCLUDE mx27_base_mem.inc
INCLUDE mx27_base_regs.inc
OPT 1 ; Reenable listing
;------------------------------------------------------------------------------
; Defines
;------------------------------------------------------------------------------
;
; ARM constants
;
ARM_CPSR_PRECISE EQU (1 << 8)
ARM_CPSR_IRQDISABLE EQU (1 << 7)
ARM_CPSR_FIQDISABLE EQU (1 << 6)
ARM_CPSR_MODE_SVC EQU 0x13
ARM_CTRL_ICACHE EQU (1 << 12)
ARM_CTRL_DCACHE EQU (1 << 2)
ARM_CTRL_MMU EQU (1 << 0)
ARM_CTRL_VECTORS EQU (1 << 13)
ARM_CACR_FULL EQU 0x3
;
; AIPI Constants
;
AIPI_PSR0_OFFSET EQU 0x0000
AIPI_PSR1_OFFSET EQU 0x0004
AIPI_PAR_OFFSET EQU 0x0008
AIPI_AAOR_OFFSET EQU 0x000C
;
; MAX Constants
;
MAX_MPR0_OFFSET EQU 0x0000
MAX_AMPR0_OFFSET EQU 0x0004
MAX_SGPCR0_OFFSET EQU 0x0010
MAX_ASGPCR0_OFFSET EQU 0x0014
MAX_MPR1_OFFSET EQU 0x0100
MAX_AMPR1_OFFSET EQU 0x0104
MAX_SGPCR1_OFFSET EQU 0x0110
MAX_ASGPCR1_OFFSET EQU 0x0114
MAX_MPR2_OFFSET EQU 0x0200
MAX_AMPR2_OFFSET EQU 0x0204
MAX_SGPCR2_OFFSET EQU 0x0210
MAX_ASGPCR2_OFFSET EQU 0x0214
MAX_MGPCR0_OFFSET EQU 0x0800
MAX_MGPCR1_OFFSET EQU 0x0900
MAX_MGPCR2_OFFSET EQU 0x0A00
MAX_MGPCR3_OFFSET EQU 0x0B00
MAX_MGPCR4_OFFSET EQU 0x0C00
MAX_MGPCR5_OFFSET EQU 0x0D00
;
; M3IF Constants
;
M3IF_M3IFCTL_OFFSET EQU 0x0000
;
; AITC constants
;
AITC_INTCNTL_OFFSET EQU 0x0000
AITC_NIMASK_OFFSET EQU 0x0004
AITC_INTENNUM_OFFSET EQU 0x0008
AITC_INTDISNUM_OFFSET EQU 0x000C
AITC_INTENABLEH_OFFSET EQU 0x0010
AITC_INTENABLEL_OFFSET EQU 0x0014
AITC_INTTYPEH_OFFSET EQU 0x0018
AITC_INTTYPEL_OFFSET EQU 0x001C
AITC_NIPRIORITY7_OFFSET EQU 0x0020
AITC_NIPRIORITY6_OFFSET EQU 0x0024
AITC_NIPRIORITY5_OFFSET EQU 0x0028
AITC_NIPRIORITY4_OFFSET EQU 0x002C
AITC_NIPRIORITY3_OFFSET EQU 0x0030
AITC_NIPRIORITY2_OFFSET EQU 0x0034
AITC_NIPRIORITY1_OFFSET EQU 0x0038
AITC_NIPRIORITY0_OFFSET EQU 0x003C
AITC_NIVECSR_OFFSET EQU 0x0040
AITC_FIVECSR_OFFSET EQU 0x0044
AITC_INTSRCH_OFFSET EQU 0x0048
AITC_INTSRCL_OFFSET EQU 0x004C
AITC_INTFRCH_OFFSET EQU 0x0050
AITC_INTFRCL_OFFSET EQU 0x0054
AITC_NIPNDH_OFFSET EQU 0x0058
AITC_NIPNDL_OFFSET EQU 0x005C
AITC_FIPNDH_OFFSET EQU 0x0060
AITC_FIPNDL_OFFSET EQU 0x0064
;
; WEIM constants
;
WEIM_CSCR0U_OFFSET EQU 0x0000
WEIM_CSCR4U_OFFSET EQU 0x0040
WEIM_CSCR0L_OFFSET EQU 0x0004
WEIM_CSCR4L_OFFSET EQU 0x0044
WEIM_CSCR0A_OFFSET EQU 0x0008
WEIM_CSCR4A_OFFSET EQU 0x0048
;
; ESDRAMC constants
;
ESDRAMC_ESDCTL0_OFFSET EQU 0x0000
ESDRAMC_ESDCFG0_OFFSET EQU 0x0004
ESDRAMC_ESDCTL1_OFFSET EQU 0x0008
ESDRAMC_ESDCFG1_OFFSET EQU 0x000C
ESDRAMC_ESDMISC_OFFSET EQU 0x0010
ESDRAMC_ESDDLY5_OFFSET EQU 0x0030
;
; RTC Constants
;
RTC_RTCCTL_OFFSET EQU 0x0010
IF :LNOT: :DEF: BOOTLOADER
GBLL BOOTLOADER
BOOTLOADER SETL {FALSE}
ENDIF
;------------------------------------------------------------------------------
; Macros
;------------------------------------------------------------------------------
;
; This macro is used to wait for a cp15 write and is needed
; when we have to ensure that the last operation to the co-pro
; was completed before continuing with operation.
;
MACRO
CPWAIT
mrc p15, 0, r0, c2, c0, 0 ; arbitrary read of cp15
mov r0, r0 ; wait for completion
sub pc, pc, #4 ; flush instruction pipeline
MEND
;------------------------------------------------------------------------------
; External Functions
;------------------------------------------------------------------------------
IMPORT OALSetUpSystemControl
IMPORT OALSetUpFrequencies
IMPORT OALSetUpGpio
IF :LNOT: BOOTLOADER
IMPORT KernelStart
ENDIF
;------------------------------------------------------------------------------
;
; Function: StartUp
;
; First routine executed on power on. Shared between EBOOT/Kernel.
;
; Normally exception vetors is placed before here but the linker always
; place a 4KB page with a branch to StartUp at the image start. So we DO NOT
; have control over the vector codes.
;
; Parameters:
; None.
;
; Returns:
; None.
;
;------------------------------------------------------------------------------
STARTUPTEXT
LEAF_ENTRY StartUp
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Put the processor in supervisor mode
; Disable the interrupt request (IRQ) and fast interrupt request (FIQ)
; inputs
;--------------------------------------------------------------------------
mrs r0, cpsr ; r0 = CPSR
mov r0, #ARM_CPSR_MODE_SVC ; enter supervisor mode
orr r0, r0, #ARM_CPSR_IRQDISABLE ; disable normal IRQ
orr r0, r0, #ARM_CPSR_FIQDISABLE ; disable fast IRQ
msr cpsr_xc, r0 ; update CPSR control bits
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Disable memory management unit (MMU) and both the instruction and data
; caches
;--------------------------------------------------------------------------
mrc p15, 0, r0, c1, c0, 0 ; r0 = system control reg
bic r0, r0, #ARM_CTRL_ICACHE ; disable ICache
bic r0, r0, #ARM_CTRL_DCACHE ; disable DCache
bic r0, r0, #ARM_CTRL_MMU ; disable MMU
bic r0, r0, #ARM_CTRL_VECTORS ; set vector base to 0x00000000
mcr p15, 0, r0, c1, c0, 0 ; update system control reg
;
; Set up AIPI registers for module access.
; PSR[1:0]: 10 = 32bit, 01 = 16bit, 00 = 8bit.
; PAR: 1 = Supervisor access only, 0 = Access rights is up to peripheral.
; AAOR: 1 = Atomic access only, 0 = Accept non-atomic access.
;
; AIPI1 settings:
; PSR[0]: 0x20040304
; PSR[1]: 0xDFFBFCFB (16-bit: WDOG, KPP, OWIRE, I2C)
; PAR: 0x00000001
; AAOR: 0x00000001 (reset value)
;
ldr r1, =CSP_BASE_REG_PA_AIPI1
ldr r0, =0x20040304
str r0, [r1, #AIPI_PSR0_OFFSET]
ldr r0, =0xDFFBFCFB
str r0, [r1, #AIPI_PSR1_OFFSET]
ldr r0, =0x00000001
str r0, [r1, #AIPI_PAR_OFFSET]
;
; AIPI2 settings:
; PSR[0]: 0x07FFC200
; PSR[1]: 0xFFFFFFFF
; PAR: 0xF8003D01
; AAOR: 0x00000001 (reset value)
;
ldr r1, =CSP_BASE_REG_PA_AIPI2
ldr r0, =0x07FFC200
str r0, [r1, #AIPI_PSR0_OFFSET]
ldr r0, =0xFFFFFFFF
str r0, [r1, #AIPI_PSR1_OFFSET]
ldr r0, =0xF8003D01
str r0, [r1, #AIPI_PAR_OFFSET]
;
; Set up MAX registers:
;
; MX27 MAX Master/Slave port assigments:
; Master0: I-AHB
; Master1: D-AHB/NEXUS (D-AHB is higher priority)
; Master2: LCDC/GACC
; Master3: SAHARA/USBOTG
; Master4: DMA
; Master5: eMMA
;
; Slave0: Primary AHB
; Slave1: CSI
; Slave2: BMI (TODO: No BMI on MX27!!)
; Slave3: EMI/SDRAMC (TODO: No Slave3 on MX27!!)
;
; Master Priority Register (0 - highest, 7 - lowest)
; MPR0: 0x77123045
; MPR1: 0x77123045
; MPR2: 0x77123045
; MPR3: 0x77123045
;
; Alternate Master Priority Register
; AMPR0: 0x77123045
; AMPR1: 0x77123045
; AMPR2: 0x77123045
; AMPR3: 0x77123045
;
; Slave General Purpose Control Register
; SGPCR0: 0x00000010 (Park on last master)
; SGPCR1: 0x00000005 (Park on eMMA)
; SGPCR2: 0x00000010 (Park on last master)
; SGPCR3: 0x00000002 (Park on LCDC)
;
; Alternate Slave General Purpose Control Register
; ASGPCR0: 0x00000010 (Park on last master)
; ASGPCR1: 0x00000005 (Park on eMMA)
; ASGPCR2: 0x00000010 (Park on last master)
; ASGPCR3: 0x00000002 (Park on LCDC)
;
; Master General Purpose Control Register
; MGPCR0: 0x00000001 (Arbitration allowed at any time during an undefined length burst)
; MGPCR1: 0x00000001 (Arbitration allowed at any time during an undefined length burst)
; MGPCR2: 0x00000000 (No arbitration allowed during an undefined length burst)
; MGPCR3: 0x00000001 (Arbitration allowed at any time during an undefined length burst)
; MGPCR4: 0x00000001 (Arbitration allowed at any time during an undefined length burst)
; MGPCR5: 0x00000001 (Arbitration allowed at any time during an undefined length burst)
;
ldr r1, =CSP_BASE_REG_PA_MAX
;
; Master Priority Register
;
ldr r0, =0x77123045
str r0, [r1, #MAX_MPR0_OFFSET]
str r0, [r1, #MAX_AMPR0_OFFSET]
str r0, [r1, #MAX_MPR1_OFFSET]
str r0, [r1, #MAX_AMPR1_OFFSET]
str r0, [r1, #MAX_MPR2_OFFSET]
str r0, [r1, #MAX_AMPR2_OFFSET]
;; str r0, [r1, #MAX_MPR3_OFFSET]
;; str r0, [r1, #MAX_AMPR3_OFFSET]
;
; Slave General Purpose Control Register
;
ldr r0, =0x00000010
str r0, [r1, #MAX_SGPCR0_OFFSET]
str r0, [r1, #MAX_ASGPCR0_OFFSET]
ldr r0, =0x00000005
str r0, [r1, #MAX_SGPCR1_OFFSET]
str r0, [r1, #MAX_ASGPCR1_OFFSET]
ldr r0, =0x00000010
str r0, [r1, #MAX_SGPCR2_OFFSET]
str r0, [r1, #MAX_ASGPCR2_OFFSET]
;; ldr r0, =0x00000002
;; str r0, [r1, #MAX_SGPCR3_OFFSET]
;; str r0, [r1, #MAX_ASGPCR3_OFFSET]
;
; Master General Purpose Control Register
;
ldr r0, =0x00000000
str r0, [r1, #MAX_MGPCR2_OFFSET]
ldr r0, =0x00000001
str r0, [r1, #MAX_MGPCR0_OFFSET]
str r0, [r1, #MAX_MGPCR1_OFFSET]
str r0, [r1, #MAX_MGPCR3_OFFSET]
str r0, [r1, #MAX_MGPCR4_OFFSET]
str r0, [r1, #MAX_MGPCR5_OFFSET]
;
; Configure M3IF registers
;
; M3IF Control Register (M3IFCTL) (TODO: Need porting on MX27!!)
; MRRP[0] = TMAX not on priority list (0 << 0) = 0x00000000
; MRRP[1] = SMIF not on priority list (0 << 0) = 0x00000000
; MRRP[2] = MAX0 not on priority list (0 << 0) = 0x00000000
; MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
; MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
; MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
; MRRP[6] = IPU on priority list (1 << 6) = 0x00000040
; MRRP[7] = SMIF-L2CC not on priority list (0 << 0) = 0x00000000
; ------------
; 0x00000040
;
ldr r1, =CSP_BASE_REG_PA_M3IF
ldr r0, =0x00000040
str r0, [r1, #M3IF_M3IFCTL_OFFSET]
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