tortola_init_ddr32_v1.inc

飞思卡尔imx27 wince5.0 bootloader源代码

//*================================================================================================
//* Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
//* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
//* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
//* Freescale Semiconductor, Inc.
//*================================================================================================
// Initialization script for  Tortola EVB 
//*================================================================================================
// Revision History:
//                             Modification     Tracking
// Author (core ID)             Date D/M/Y       Number    Description of Changes
// -------------------------   ------------    ----------  ----------------------------------------
// R58931                       04-Apr-2005                 Creation of the file.
//*================================================================================================
wait = on

//*================================================================================================
// init_ccm - base freq = 532, configuring post dividers
//*================================================================================================

// plls_enable(308) + ckih //CCM_CCMR=53F80000 (assumes use of 26 MHz ref freq)
//   setmem /32 0x53F80000 = 0x074b0b7d
// set clock source for FPM
	setmem /32 0x53F80000 = 0x074b0b7b
   
// enable ipu di, to get acknowledge for max_podf value change//IPU_CONF=53FC0000
   setmem /32 0x53FC0000 = 0x040
   
//   // reconfigure Post Dividers
//   // mcu_podf=0(1), max_podf=3(4), ipg_podf=1(2), nfc_podf=5(6)
//   // other post dividers get their spec default value
//   // CCM_PDR0=53F80004
   setmem /32 0x53F80004 = 0xFF871D58
      
// set_mpll_to_532()// // reg32_write(CCM_MPCTL,0x00162002)////CCM_MPCTL=53F80010
   setmem /32 0x53F80010 = 0x00162002	// this settings assumes 32kHz, but ADS has 32.768 kHz source

// reset Delay line measurement for DDR
//setmem /32 0xB8001010 =0x0000000C	


// Dummy CAFECAFE write into PSRAM
// 
//*================================================================================================
// Configure PSRAM on CS5 
//*================================================================================================
// WEIM_CS1U  SP___WP___BCD__BCS__PSZ__PME__SYNC_DOL__CNC___WSC_______EW___WWS_____EDC
// WEIM_CS1U  1'b0_1'b0_2'b0_4'b0_2'b0_1'b0_1'b0_4'b0_2'b11_6'b011100_1'b1_3'b111__4'b0110
// user mode, no WP, no burst, 
setmem /32 0xb8002050 = 0x0000dcf6
// WEIM_CS1L  OEA__OEN__WEA__WEN__CSA__EBC__DSZ__CSN__PSR__CRE__WRAP_CSEN
// WEIM_CS1L  4'h4_4'h4_4'h4_4'ha_4'h4_1'b0_3'b5_4'h4_1'b0_1'b0_1'b0_1'b1
// 
// 
setmem /32 0xb8002054 = 0x444a4541
// WEIM_CS1A  EBA__EBN__RWA__RWN__MUM__LAH___LBN__LBA__DWW__DCT__WWU__AGE__CNC2_FCE
// WEIM_CS1A  4'h4_4'h4_4'h4_4'h4_ 1'h0_2'b01_3'b4_2'h1_1'b1_2'b0_1'b0_1'b0_1'b1_1'b0
// 
// 
setmem /32 0xb8002058 = 0x44443302
setmem /32 0xB6000000 =0xCAFECAFE 
//  ================================================================================================
//        16 bit PSRAM Initialization on CS5 completed 
//  ================================================================================================

//  =====================================================
//        Start 16 bit NorFlash Initialization on CS0
//  =====================================================

// WEIM_CS0U  SP___WP___BCD__BCS__PSZ__PME__SYNC_DOL__CNC___WSC_______EW___WWS_____EDC
// WEIM_CS0U  1'b0_1'b0_2'b0_4'b0_2'b0_1'b0_1'b0_4'b0_2'b11_6'b001100_1'b0_3'b000__4'b0011
// user mode, WP, no burst, CS_B negated for 4 clks, 14WS for read, no DTACK, 14Ws for write, 3 extra dead cycle in read 
setmem /32 0xb8002000  = 0x0000CC03
// WEIM_CS0L  OEA__OEN__WEA__WEN__CSA__EBC__DSZ__CSN__PSR__CRE__WRAP_CSEN
// WEIM_CS0L  4'ha_4'h0_4'h3_4'h3_4'h0_1'b1_3'b5_4'h0_1'b0_1'b0_1'b0_1'b1
// 
// 
setmem /32 0xb8002004  = 0xa0330D01
// WEIM_CS0A  EBA__EBN__RWA__RWN__MUM__LAH____LBN__LBA__DWW__DCT__WWU__AGE__CNC2_FCE
// WEIM_CS0A  4'h0_4'h0_4'h2_4'h2_1'h0_2'b0_3'b010_2'h0_1'b0_2'b0_1'b0_1'b0_1'b0_1'b0
// 
// 
setmem /32 0xb8002008 = 0x00220800

//  =====================================================
//        16 bit NorFlash Initialization on CS0 completed
//  ===================================================== 

//*================================================================================================
// Configure CPLD on CS4 
//*================================================================================================
// WEIM_CS4U  SP___WP___BCD__BCS__PSZ__PME__SYNC_DOL__CNC___WSC_______EW___WWS_____EDC
// WEIM_CS4U  1'b0_1'b0_2'b0_4'b0_2'b0_1'b0_1'b0_4'b0_2'b11_6'b010000_1'b0_3'b100__4'b0010
// user mode, no WP, no burst, CS_B negated for 4 clks, 32WS for read, no DTACK, 36Ws for write, 2 extra dead cycle in read 
setmem /32 0xb8002040 = 0x0000d042
// WEIM_CS4L  OEA__OEN__WEA__WEN__CSA__EBC__DSZ__CSN__PSR__CRE__WRAP_CSEN
// WEIM_CS4L  4'h1_4'h1_4'h1_4'h1_4'h1_1'b0_3'b5_4'h1_1'b0_1'b0_1'b0_1'b1
// OE_B and WE_B are assrted half cycle after 1/2 clk and negated 1/2 clk before end, CS assrted 1/2 after add and negated 1/2 clk befor add.
// EB for both Rd & Wr, 16bit data, PSRAM disabled, Control register disabled, no wrap, CS enabled
setmem /32 0xb8002044 = 0x11111511
// WEIM_CS4A  EBA__EBN__RWA__RWN__MUM__LAH___LBN__LBA__DWW__DCT__WWU__AGE__CNC2_FCE
// WEIM_CS4A  4'h1_4'h1_4'h1_4'h1_1'h0_2'b01_3'b0_2'h1_1_b0_2'b0_1'b0_1'b0_1'b0_1'b0
// EB_B and RW_B are assrted half cycle after 1/2 clk and negated 1/2 clk before end, no mux mode, add. held 1 clk after LBA
// LBA negated at end of access and asserted 1/2 cycle after access start, data captuted on AHB clk
setmem /32 0xb8002048 = 0x11112100


//*================================================================================================
// Initialization script for 32 bit DDR (Full Page mode) on Tortola EVB 
//*================================================================================================
wait = on
// ESD_ESDMISC 29'b0_MDDREN_RST__1'b0
// ESD_ESDMISC 29'b0__1'b1__1'b0_1'b0
// enable DDR mode
setmem /32 0xB8001010 =0x00000004
// @//timming config(infineon): XP__WTR__RP_MRD_WR__RAS_RRD_CL___RCD__RC
// @//ESD_ESDCFG0=          32'b11___0___10__10__1__100__01_11_0_011_1010
setmem /32 0xB8001004 =0x006ac73a
// ESD_ESDCTL0  SDE_SMODE_SP_ROW_00_COL_00_DSIZ_SREFR_0_PWDT_0_FP_BL_0__PRCT
// ESD_ESDCTL0 32'b1_001__0__010_00__01_00___00___000_0___00_0__0__0_0_00000
// enable CS0 precharge command 
setmem /32 0xB8001000 =0x92100000
// precharge all dummy write only address matter
setmem /32 0x80000400 =0x12344321
// ESD_ESDCTL0  SDE_SMODE_SP_ROW_00_COL_00_DSIZ_SREFR_0_PWDT_0_FP_BL_0__PRCT
// ESD_ESDCTL0 32'b1_010__0__010_00__01_00___00___000_0___00_0__0__0_0_00000
// enable CS0 Auto-Refresh command 
setmem /32 0xB8001000 =0xa2100000
// two refresh command dummy write only address matter
setmem /32 0x80000000 =0x12344321
setmem /32 0x80000000 =0x12344321
// ESD_ESDCTL0  SDE_SMODE_SP_ROW_00_COL_00_DSIZ_SREFR_0_PWDT_0_FP_BL_0__PRCT
// ESD_ESDCTL0 32'b1_011__0__010_00__01_00___00___000_0___00_0__0__0_0_00000
// enable CS0 Load Mode Register command 
setmem /32 0xB8001000 =0xb2100000
//  dummy write only address matter
setmem /8 0x80000033 =0xda
//  dummy write only address matter
setmem /8 0x81000000 =0xff
// ESD_ESDCTL0  SDE_SMODE_SP_ROW_00_COL_00_DSIZ_SREFR_0_PWDT_0_FP_BL_0__PRCT
// ESD_ESDCTL0 32'b1_000__0__010_00__10_00___10___011_0___00_0__0__0_0_000000
// @//normal mode row=010//col=10//dzize=10//self ref=011//PWDT =00//BL =0//prct =000000
setmem /32 0xB8001000 =0x82226080
// disable precharge timer setmem /32 0xB8001000 =0x82226007
setmem /32 0x80000000 =0x0000

//  @@ configure the data abort not to be precise
setreg @CPSR_A=0

// configure AIPS1
setmem /32 0x43F00040 =0x0  // AIPS1_OPACR0_7
setmem /32 0x43F00044 =0x0  // AIPS1_OPACR8_15
setmem /32 0x43F00048 =0x0  // AIPS1_OPACR16_23
setmem /32 0x43F0004C =0x0  // AIPS1_OPACR24_31
setmem /32 0x43F00050 =0x0  // AIPS1_OPACR32_33

setmem /32 0x43F00000 =0x77777777  // AIPS1_MPROT0_7
setmem /32 0x43F00004 =0x77777777  // AIPS1_MPROT8_15

// configure AIPS2
setmem /32 0x53F00040 =0x0  // AIPS2_OPACR0_7
setmem /32 0x53F00044 =0x0  // AIPS2_OPACR8_15
setmem /32 0x53F00048 =0x0  // AIPS2_OPACR16_23
setmem /32 0x53F0004C =0x0  // AIPS2_OPACR24_31
setmem /32 0x53F00050 =0x0  // AIPS2_OPACR32_33

setmem /32 0x53F00000 =0x77777777  // AIPS2_MPROT0_7
setmem /32 0x53F00004 =0x77777777  // AIPS2_MPROT8_15

// configuring CP15 for enabling the pripheral bus
setreg @CP15_PERIP_MEM_REMAP=0x40000015


//*================================================================================================
// init_ccm - base freq = 400, configuring post dividers
//*================================================================================================

//setmem /32 0x53F80000 = 0x074b0b7d
//setmem /32 0x53FC0000 = 0x040
//setmem /32 0x53F80004 = 0xFF871550 // CCM_PDR0=0xFF871550
//setmem /32 0x53F80010 = 0x00011401 // CCM_MPCTL=0x00011401 - freq = 400