📄 c_common.s
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@ ---------------------------------------------------------------
@ This confidential and proprietary software may be used only as
@ authorised by a licensing agreement from FREESCALE INC
@ (C) COPYRIGHT 2005 FREESCALE INC
@ ALL RIGHTS RESERVED
@ The entire notice above must be reproduced on all authorised
@ copies and copies may only be made to the extent permitted
@ by a licensing agreement from FREESCALE INC.
@ ---------------------------------------------------------------
@
.include "as_io.tsk"
.include "as_memory_map.equ"
.include "c_macro.s"
.include "aitcv.s"
@------------------------------------------------------------------------------;
.macro INIT_VECTOR
label:
@Areas are placed in memory in alphabetical order. As we want this
@area to be first the first character is a space (' ').
.section " Vectors", "x"
@ ldr r0,=RESET_HANDLER @ 0x0 Reset
@ ldr r1,=0xfffffffc
@ str r0, [r1]
ldr r0,=UNDEF_HANDLER @ 0x4 Undef
ldr r1,=0xfffffef0
str r0, [r1]
ldr r0,=SWI_HANDLER @ 0x8 SWI
ldr r1,=0xfffffef4
str r0, [r1]
ldr r0,=PREFETCH_HANDLER @ 0xc Program abort
ldr r1,=0xfffffef8
str r0, [r1]
ldr r0,=ABORT_HANDLER @ 0x10 Data abort
ldr r1,=0xfffffefc
str r0, [r1]
@ ldr r0,=ADDR_HANDLER @ 0x14 Address exception
@ ldr r1,=0xffffffe8
@ str r0, [r1]
nop
nop
nop
nop
ldr r0,=IRQ_HANDLER @ 0x18 Irq interrupt
ldr r1,=0xffffff00
str r0, [r1]
ldr r0,=FIQ_HANDLER @ 0x1c Fiq interrupt
ldr r1,=0xffffff04
str r0, [r1]
ldr pc,=RESET_HANDLER
.ltorg
FIQ_HANDLER:
STMFD sp!, {r0-r12,lr} @ Push registers on stack
LDR r0, =AITC_FIVECSR @ Fast Interrupt vector & status
LDR r1, [r0, #0x0] @ Read vector
LDR r0,=AITC_FVR
MOV lr, pc
LDR pc,[r0, r1, LSL #2]
LDMFD sp!, {r0-r12,lr} @ Pop registers from stack
SUBS pc, r14, #4 @ Return from Irq
.ltorg
IRQ_HANDLER:
STMFD sp!, {r0-r12,lr} @ Push registers on stack
LDR r0, =AITC_NIVECSR @ Normal Interrupt vector & status
LDR r1, [r0, #0x0] @ Read vector
MOV r1, r1,LSR #16 @ Shift right NIVECTOR[31:16] to [15:0]
LDR r0,=AITC_IVR
MOV lr, pc
LDR pc,[r0, r1, LSL #2]
LDMFD sp!, {r0-r12,lr} @ Pop registers from stack
SUBS pc, r14, #4 @ Return from Irq
.ltorg
ADDR_HANDLER:
MOVS pc,lr
.ltorg
ABORT_HANDLER:
WRITE ABT_DATA_PH, 0x0
@SUBS pc,lr,#8
SUBS pc,lr,#4
.ltorg
PREFETCH_HANDLER:
WRITE ABT_PREFETCH_PH, 0x0
SUBS pc,lr,#4
.ltorg
SWI_HANDLER:
MOVS pc,lr
.ltorg
UNDEF_HANDLER:
WRITE ABT_UNDEF_PH, 0x0
MOVS pc,lr
.ltorg
.endm @ INIT_VECTOR
@------------------------------------------------------------------------------;
@ Macro to initialize Stack Pointerat SDRAM0 s and enable interrupts
@------------------------------------------------------------------------------;
.macro INIT_SDRAM0_STACK
INIT_WEIM
@Enter FIQ Mode and set up its stack
MRS r0, CPSR @get CPSR onto r0
BIC r0, r0, #MODE_BITS @Bit clear [31:5]
ORR r1, r0, #MODE_FIQ
MSR CPSR_c, r1 @Enter FIQ Mode
MOV r2, #MODE_FIQ
MSR SPSR_c, r2 @Set SPSR to FIQ Mode
ldr sp, =FIQ_SDRAM0_STACK @Setup FIQ stack pointer
@Enter IRQ Mode and set up its stack
MRS r0, CPSR @get CPSR onto r0
BIC r0, r0, #MODE_BITS @Bit clear [31:5]
ORR r1, r0, #MODE_IRQ
MSR CPSR_c, r1 @Enter IRQ Mode
MOV r2, #MODE_IRQ
MSR SPSR_c, r2 @Set SPSR to IRQ Mode
ldr sp, =IRQ_SDRAM0_STACK @Setup IRQ stack pointer
@ Enter Privilledge Mode and set up the SVC stack pointer
MRS r0, CPSR @get CPSR onto r0
BIC r0, r0, #MODE_BITS @Bit clear [31:5]
ORR r1, r0, #MODE_SVC
MSR CPSR_c, r1 @Enter SVC Mode
MOV r2, #MODE_SVC
MSR SPSR_c, r2 @Set SPSR to Privilledge Mode
ldr sp, =SVC_SDRAM0_STACK @Setup Privillege stack pointer
@ Enable FIQ and IRQ
MRS r0, CPSR @get CPSR onto r0
AND r1, r0, #(ENABLE_IRQ+ENABLE_FIQ+MODE_BITS)
MSR CPSR_c, r1 @Enter SVC Mode
.endm
@------------------------------------------------------------------------------;
@ Macro to initialize Stack Pointers at SDRAM1 and enable interrupts
@------------------------------------------------------------------------------;
.macro INIT_SDRAM1_STACK
INIT_WEIM
@Enter FIQ Mode and set up its stack
MRS r0, CPSR @get CPSR onto r0
BIC r0, r0, #MODE_BITS @Bit clear [31:5]
ORR r1, r0, #MODE_FIQ
MSR CPSR_c, r1 @Enter FIQ Mode
MOV r2, #MODE_FIQ
MSR SPSR_c, r2 @Set SPSR to FIQ Mode
ldr sp, =FIQ_SDRAM1_STACK @Setup FIQ stack pointer
@Enter IRQ Mode and set up its stack
MRS r0, CPSR @get CPSR onto r0
BIC r0, r0, #MODE_BITS @Bit clear [31:5]
ORR r1, r0, #MODE_IRQ
MSR CPSR_c, r1 @Enter IRQ Mode
MOV r2, #MODE_IRQ
MSR SPSR_c, r2 @Set SPSR to IRQ Mode
ldr sp, =IRQ_SDRAM1_STACK @Setup IRQ stack pointer
@ Enter Privilledge Mode and set up the SVC stack pointer
MRS r0, CPSR @get CPSR onto r0
BIC r0, r0, #MODE_BITS @Bit clear [31:5]
ORR r1, r0, #MODE_SVC
MSR CPSR_c, r1 @Enter SVC Mode
MOV r2, #MODE_SVC
MSR SPSR_c, r2 @Set SPSR to Privilledge Mode
ldr sp, =SVC_SDRAM1_STACK @Setup Privillege stack pointer
@ Enable FIQ and IRQ
MRS r0, CPSR @get CPSR onto r0
AND r1, r0, #(ENABLE_IRQ+ENABLE_FIQ+MODE_BITS)
MSR CPSR_c, r1 @Enter SVC Mode
.endm
@------------------------------------------------------------------------------;
@ Macro to initialize Stack Pointers at SRAM and enable interrupts
@------------------------------------------------------------------------------;
.macro INIT_SRAM_STACK
INIT_WEIM
@Enter FIQ Mode and set up its stack
MRS r0, CPSR @get CPSR onto r0
BIC r0, r0, #MODE_BITS @Bit clear [31:5]
ORR r1, r0, #MODE_FIQ
MSR CPSR_c, r1 @Enter FIQ Mode
MOV r2, #MODE_FIQ
MSR SPSR_c, r2 @Set SPSR to FIQ Mode
ldr sp, =FIQ_SRAM_STACK @Setup FIQ stack pointer
@Enter IRQ Mode and set up its stack
MRS r0, CPSR @get CPSR onto r0
BIC r0, r0, #MODE_BITS @Bit clear [31:5]
ORR r1, r0, #MODE_IRQ
MSR CPSR_c, r1 @Enter IRQ Mode
MOV r2, #MODE_IRQ
MSR SPSR_c, r2 @Set SPSR to IRQ Mode
ldr sp, =IRQ_SRAM_STACK @Setup IRQ stack pointer
@ Enter Privilledge Mode and set up the SVC stack pointer
MRS r0, CPSR @get CPSR onto r0
BIC r0, r0, #MODE_BITS @Bit clear [31:5]
ORR r1, r0, #MODE_SVC
MSR CPSR_c, r1 @Enter SVC Mode
MOV r2, #MODE_SVC
MSR SPSR_c, r2 @Set SPSR to Privilledge Mode
ldr sp, =SVC_SRAM_STACK @Setup Privillege stack pointer
@ Enable FIQ and IRQ
MRS r0, CPSR @get CPSR onto r0
AND r1, r0, #(ENABLE_IRQ+ENABLE_FIQ+MODE_BITS)
MSR CPSR_c, r1 @Enter SVC Mode
.endm
@------------------------------------------------------------------------------;
.macro INIT_AIPI1
@ Initialize all peripheral in AIPI1 PSR[1:0] => 10=32bit, 01=16bit, 00=8bit
LDR r1, =AIPI1_BASE_ADDR @ AIPI 1 base address
@ PSR[0]
LDR r2, =0x20040304 @
STR r2, [r1,#0x0] @
@ PSR[1]
LDR r2, =0xDFFBFCFB
STR r2, [r1,#0x4] @
@ Allow either user or supervisor access to AIPI1 peripherals
@LDR r2, =0x00000000 @ Allow supervisor & user access
@STR r2, [r1,#0x8]
@ use CS1 instead of GPIO
LDR r1, =GPIOF_GIUS @ GPIO in use
LDR r2, =0x00000000 @ turn off
STR r2, [r1,#0x0] @
.endm
@------------------------------------------------------------------------------;
.macro INIT_AIPI2
@ Initialize all peripheral in AIPI1 PSR[1:0] => 10=32bit, 01=16bit, 00=8bit
@ LDR r1, =AIPI2_BASE_ADDR @ AIPI 2 base address
@ LDR r2, =0x00000400 @ mshc 16 bits
@ STR r2, [r1,#0x0] @ PSR[0]=0
@ LDR r2, =0xFFFFFbFF @ mshc 16 bits
@ STR r2, [r1,#0x4] @ PSR[1]=1
LDR r1, =AIPI2_BASE_ADDR @ AIPI 2 base address
@ PSR[0]
LDR r2, =0x07FFC200 @
STR r2, [r1,#0x0] @
@ PSR[1]
LDR r2, =0xFFFFFFFF @
STR r2, [r1,#0x4]
@ Allow either user or supervisor access to AIPI2 peripherals
@LDR r2, =0x00000000 @ Allow supervisor & user access
@STR r2, [r1,#0x8]
INIT_CLK
.endm
@------------------------------------------------------------------------------;
.macro INIT_WEIM
@ Enable Chip select for CS1..CS5
EN_CS:
LDR r1, =WEIM_CS0U @ Chip Sel 0 Control Reg
LDR r2, =0x00000000 @
STR r2, [r1,#0x8] @ WEIM_CS0A change reset value to fast
LDR r2, =0x00200501 @ enable CS0 and 16-bit ports
STR r2, [r1,#0x4] @ change WEIM_CS0L
LDR r2, =0x00000200 @ Wait State Control = 2
STR r2, [r1,#0x0] @ PSR[0]=0 WEIM_CS0U
LDR r1, =WEIM_CS5U
LDR r2, =0x00000001 @ CSEN5=1 Enable Chip Select
STR r2, [r1,#0x4] @ WEIM_CS5L
LDR r2, =0x00000200 @ ADD wait state due to timing violations
STR r2, [r1,#0x0] @ WEIM_CS5U
LDR r1, =WEIM_CS1U
LDR r2, =0x00000200 @ 2 Wait States for read/write
STR r2, [r1,#0x0]
LDR r1, =WEIM_CS1L
LDR r2, =0x00200501 @
STR r2, [r1,#0x0]
NOP
NOP
NOP
NOP
@ ADD PC, PC,#0x10000000
@ nop
@ if {ENDIAN}="big"
@ bigend
@ endif
.endm
@------------------------------------------------------------------------------;
@ macro to default crm to full speed
.macro INIT_CLK
LDR r1, =CRM_CSCR @ Clock Source Control Reg
LDR r2, [r1,#0x0]
LDR r0, =0xFFFF01FF @ mask off prescaler bits
AND r4, r2, r0
LDR r0, =0x00000200
ORR r5, r4, r0
STR r5, [r1,#0x0]
LDR r1, =SYS_GPCR
LDR r2, [r1,#0x0]
LDR r0, =0x00000700
ORR r2, r2, r0
STR r2, [r1,#0x0]
.endm
@----------------------------------------------------------------------------
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