upsd3300.h

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/*--------------------------------------------------------------------------
uPSD3300.H

Header file for STM 3300 Turbo MicroPSD (uPSD) microcontroller.
03/2003 Ver 0.1 - Initial Version

Copyright (c) 2003 ST Microelectronics
This example demo code is provided as is and has no warranty,
implied or otherwise.  You are free to use/modify any of the provided
code at your own risk in your applications with the expressed limitation
of liability (see below) so long as your product using the code contains
at least one uPSD products (device).

LIMITATION OF LIABILITY:   NEITHER STMicroelectronics NOR ITS VENDORS OR 
AGENTS SHALL BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
--------------------------------------------------------------------------*/

/*--------------------------------------------------------------------------
Revise:
1. SCON1 is bit addressable.
2. delete suffix '1' in SCON0 bit signals.
2. Interrupt number is not interrupt priority.
--------------------------------------------------------------------------*/


#ifndef _UPSD_H_
#define _UPSD_H_


typedef struct	// general structure of 8 bit register allowing bit access 
	{
	unsigned char bit0 : 1;
	unsigned char bit1 : 1;
	unsigned char bit2 : 1;
	unsigned char bit3 : 1;
	unsigned char bit4 : 1;
 	unsigned char bit5 : 1;
	unsigned char bit6 : 1;
	unsigned char bit7 : 1;
	} Register;    

typedef union	// allow bit or byte access to registers 
	{
	char byte;
	Register bits;
	} xdata Mix_Reg;

typedef union	// allow bit or byte access to registers 
	{
	char byte;
	Register bits;
	} SFR_Reg;


/* ------------------------------ */
/*      Standard PSD Registers    */
/* ------------------------------ */

typedef xdata struct REG_PSD_struct {
        unsigned char DATAIN_A;         // PSD_REG_BASE +0x00
        unsigned char DATAIN_B;         //              +0x01
        unsigned char CONTROL_A;        //              +0x02
        unsigned char CONTROL_B;        //              +0x03
        unsigned char DATAOUT_A;        //              +0x04
        unsigned char DATAOUT_B;        //              +0x05
        unsigned char DIRECTION_A;      //              +0x06
        unsigned char DIRECTION_B;      //              +0x07
        unsigned char DRIVE_A;          //              +0x08
        unsigned char DRIVE_B;          //              +0x09
        unsigned char IMC_A;            //              +0x0A
        unsigned char IMC_B;            //              +0x0B
        unsigned char OUTENABLE_A;      //              +0x0C
        unsigned char OUTENABLE_B;      //              +0x0D
        unsigned char res2[2];          //      spacer
        unsigned char DATAIN_C;         //              +0x10
        unsigned char DATAIN_D;         //              +0x11
        unsigned char DATAOUT_C;        //              +0x12 
        unsigned char DATAOUT_D;        //              +0x13
        unsigned char DIRECTION_C;      //              +0x14
        unsigned char DIRECTION_D;      //              +0x15
        unsigned char DRIVE_C;          //              +0x16
        unsigned char DRIVE_D;          //              +0x17
        unsigned char IMC_C;            //              +0x18
        unsigned char res1a;            //      spacer
        unsigned char OUTENABLE_C;      //              +0x1A
        unsigned char OUTENABLE_D;      //              +0x1B
        unsigned char res4[4];          //      spacer
        unsigned char OMC_AB;           //              +0x20
        unsigned char OMC_BC;           //              +0x21
        unsigned char OMCMASK_AB;       //              +0x22
        unsigned char OMCMASK_BC;       //              +0x23
        unsigned char res8c[0x8C];      //      spacer
        unsigned char PMMR0;            //              +0xB0
        unsigned char res1b;            //      spacer
        unsigned char PMMR1;            //              +0xB2
        unsigned char res1c;            //      spacer
        unsigned char PMMR2;            //              +0xB4
        unsigned char res0B[0x0B];      //      spacer
        unsigned char MAINPROTECT;      //              +0xC0
        unsigned char res1d;            //      spacer
        unsigned char ALTPROTECT;       //              +0xC2
        unsigned char res4a[4];         //      spacer
        unsigned char JTAG;             //              +0xC7
        unsigned char res18[0x18];      //      spacer
        unsigned char PAGE;             //              +0xE0
        unsigned char res1e;            //      spacer
        unsigned char VM;               //              +0xE2
	  unsigned char res29[0x1d];	    //    	spacer
} PSD_REGS;




//****************** PSD control register bit definitions *********

//PSD PORTA
#define PA0		bit0
#define PA1		bit1	
#define PA2		bit2	
#define PA3		bit3	
#define PA4		bit4	
#define PA5		bit5	
#define PA6		bit6	
#define PA7		bit7	

//PSD PORTB
#define PB0		bit0
#define PB1		bit1	
#define PB2		bit2	
#define PB3		bit3	
#define PB4		bit4	
#define PB5		bit5	
#define PB6		bit6	
#define PB7		bit7	

//PSD PORTC
#define PC0		bit0
#define PC1		bit1	
#define PC2		bit2	
#define PC3		bit3	
#define PC4		bit4	
#define PC5		bit5	
#define PC6		bit6	
#define PC7		bit7	

//PSD PORTD
#define PD0		bit0
#define PD1		bit1	
#define PD2		bit2	

//PSD JTAG
#define JEN		bit0   // JTAG enable

//PSD PMMR0
#define APD_ENABLE	    bit1
#define PLD_TURBO		bit3
#define PLD_ARRAY_CLK	bit4
#define PLD_MCELL_CLK	bit5

//PSD PMMR2
#define PLD_CNTL0		bit2
#define PLD_CNTL1		bit3
#define PLD_CNTL2		bit4
#define PLD_ALE		    bit5
#define PLD_DBE		    bit6

//PSD VM
#define SRAM_CODE		bit0
#define EE_CODE		    bit1
#define FL_CODE		    bit2
#define EE_DATA		    bit3
#define FL_DATA		    bit4
#define PIO_EN		    bit7


// Common Misc. Defines...
#ifndef TRUE
  #define TRUE 0x01
#endif 
#ifndef FALSE
  #define FALSE 0x00
#endif 
#ifndef ON
  #define ON 0x01
#endif 
#ifndef OFF
  #define OFF 0x00
#endif 
#ifndef NULL
  #define NULL 0x00
#endif 



/* ------------------------------ */
/* Standard 8051 MCU Registers    */
/* ------------------------------ */
// sfr P0       = 0x80;	// Port 0 - Always used for External Memory Access (no access)
sfr P1        = 0x90;	// Port 1
// sfr P2       = 0xA0;	// Port 2 - Always used for External Memory Access (no access)
sfr P3        = 0xB0;  	// Port 3
sfr PSW       = 0xD0;  	// Program Status Word
sfr ACC       = 0xE0;  	// Accumulator
sfr B         = 0xF0;  	// Register B
sfr SP        = 0x81;  	// Stack Pointer
sfr DPL       = 0x82;  	// Data Pointer low byte
sfr DPH       = 0x83;  	// Data Pointer high byt
sfr PCON      = 0x87;  	// MCU Power Control Register
sfr TCON      = 0x88;  	// Timer / Counter Control
sfr TMOD      = 0x89;  	// Timer / Counter Mode
sfr TL0       = 0x8A;  	// Timer 0 low byte
sfr TL1       = 0x8B;  	// Timer 1 low byte
sfr TH0       = 0x8C;  	// Timer 0 high byte
sfr TH1       = 0x8D;  	// Timer 1 high byte
sfr IE        = 0xA8;  	// Interrupt Enable (main)
sfr IP        = 0xB8;  	// Interrupt Priority (main) 
sfr SCON     = 0x98;  	// UART0 Serial Control
sfr SBUF     = 0x99;  	// UART0 Serial Buffer
sfr BUSCON   = 0x9D;    // Bus Control Register

/* ------------------------ */
/*  Common 8052 Extensions  */
/* ------------------------ */
sfr T2CON     = 0xC8;	// Timer 2 Control
sfr RCAP2L    = 0xCA;	// Timer 2 Reload low byte
sfr RCAP2H    = 0xCB;	// Timer 2 Reload high byte
sfr TL2       = 0xCC;	// Timer 2 low byte
sfr TH2       = 0xCD;	// Timer 2 high byte

/* ------------------------ */
/*  UPSD 3300 Extensions    */
/* ------------------------ */
sfr P4        = 0xC0;	// New port 4
sfr P1SFS0    = 0x8E;	// Port 1 I/O select Register 0
sfr P1SFS1    = 0x8F;	// Port 1 I/O select Register 1
sfr P3SFS     = 0x91;	// Port 3 I/O select
sfr P4SFS0    = 0x92;	// Port 4 I/O select Register 0
sfr P4SFS1    = 0x93;	// Port 4 I/O select Register 1

// --- ADC SFRs ---
sfr ADCPS    = 0x94;	// ADC Clock Control Register
sfr ADAT0    = 0x95;	// ADC Data Register1 ADAT[9:8]
sfr ADAT1    = 0x96;	// ADC Data Register0 ADAT[7:0]
sfr ACON     = 0x97;	// ADC Control Register

// --- UART1 SFRS ----
sfr SCLK1    = 0xD1;	// UART1 Serial Clock
sfr SCON1    = 0xD8;	// UART1 Serial Control
sfr SBUF1    = 0xD9;	// UART1 Serial Buffer

// --- PCA SFRs ------
sfr PCACL0   = 0xA2;	// PCA0 Counter Low
sfr PCACH0   = 0xA3;	// PCA0 Counter High
sfr PCACON0  = 0xA4;	// PCA0 Configuration Register
sfr PCASTA   = 0xA5;	// PCA0, PCA1 Status Register
sfr PCACL1   = 0xBA;	// PCA1 Counter Low
sfr PCACH1   = 0xBB;	// PCA1 Counter High
sfr PCACON1  = 0xBC;	// PCA1 Configuration Register 
sfr PWMF0    = 0xB4;    // PCA0 PWM Frequency
sfr PWMF1    = 0xC7;    // PCA1 PWM Frequency


// ---TCM SFRs -------
sfr TCMMODE0  = 0xA9;   // TCM0 Mode Register   
sfr TCMMODE1  = 0xAA;   // TCM1 Mode Register   
sfr TCMMODE2  = 0xAB;   // TCM2 Mode Register
sfr TCMMODE3  = 0xBD;   // TCM3 Mode Register
sfr TCMMODE4  = 0xBE;   // TCM4 Mode Register
sfr TCMMODE5  = 0xBF;   // TCM5 Mode Register
sfr CAPCOML0  = 0xAC;   // TCM0 Capture/Compare Register Low  
sfr CAPCOMH0  = 0xAD;   // TCM0 Capture/Compare Register High  
sfr CAPCOML1  = 0xAF;   // TCM1 Capture/Compare Register Low  
sfr CAPCOMH1  = 0xB1;   // TCM1 Capture/Compare Register High  
sfr CAPCOML2  = 0xB2;   // TCM2 Capture/Compare Register Low  
sfr CAPCOMH2  = 0xB3;   // TCM2 Capture/Compare Register High 
sfr CAPCOML3  = 0xC1;   // TCM3 Capture/Compare Register Low  
sfr CAPCOMH3  = 0xC2;   // TCM3 Capture/Compare Register High 
sfr CAPCOML4  = 0xC3;   // TCM4 Capture/Compare Register Low  
sfr CAPCOMH4  = 0xC4;   // TCM4 Capture/Compare Register High 
sfr CAPCOML5  = 0xC5;   // TCM5 Capture/Compare Register Low  
sfr CAPCOMH5  = 0xC6;   // TCM5 Capture/Compare Register High 
 

// --- WDT SFRs ---
sfr WDRST    = 0xA6;    // Watch Dog Reset
sfr WDKEY    = 0xAE;    // Watch Dog Key Enable

// --- INTERRUPT 2 SFRs ---
sfr IEA      = 0xA7;   	// Interrupt Enable (2nd)
sfr IPA      = 0xB7;    // Interrupt Priority (2nd)

// --- I2C SFRs ---
sfr S1SETUP  = 0XDB;    // I2C S1 Setup
sfr S1CON    = 0xDC;	// I2C Bus Control Register
sfr S1STA    = 0xDD;	// I2C Bus Status
sfr S1DAT    = 0xDE;	// I2C Data Hold Register
sfr S1ADR    = 0xDF;    // I2C Bus Address

// --- SPI SFRs ----
sfr SPICLKD  = 0XD2;    // SPI Clock Divisor
sfr SPISTAT  = 0XD3;    // SPI Status Reg.
sfr SPITDR   = 0xD4;    // SPI Transmit Reg.
sfr SPIRDR   = 0xD5;    // SPI Receive Reg.