rs232.v

FPGA实现RS-232串口收发的Verilog程序

发送端：
module trans(clk,
             rst,
             TxD_start,
             TxD_data,
             TxD,
             TxD_busy
             );
input      clk,
           rst,
           TxD_start;
input[7:0] TxD_data;   // 待发送的数据
output     TxD,        // 输出端口发送的串口数据
           TxD_busy;   

reg        TxD;
reg [7:0]  TxD_dataReg;   // 寄存器发送模式，因为在串口发送过程中输入端不可能一直保持有效电平
reg [3:0]  state;
parameter  ClkFrequency = 25000000;  // 时钟频率－25 MHz
parameter  Baud = 115200;            // 串口波特率－115200 


// 波特率产生
parameter BaudGeneratorAccWidth = 16;
reg       [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always @(posedge clk or negedge rst)
   if(~rst)
      BaudGeneratorAcc <= 0;
 else if(TxD_busy)
    BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;

// 发送端状态
wire   TxD_ready = (state==0);  // 当state = 0时，处于准备空闲状态，TxD_ready = 1
assign TxD_busy = ~TxD_ready;   // 空闲状态时TxD_busy = 0

// 把待发送数据放入缓存寄存器 TxD_dataReg
always @(posedge clk or negedge rst)
   if(~rst)
      TxD_dataReg <= 8'b00000000;
 else if(TxD_ready & TxD_start)
  TxD_dataReg <= TxD_data;   
  
// 发送状态机
always @(posedge clk or negedge rst)
 if(~rst)
      begin
         state <= 4'b0000;   // 复位时，状态为0000，发送端一直发1电平
         TxD <= 1'b1;
      end
 else 
 case(state)
  4'b0000: if(TxD_start) begin
                      state <= 4'b0100; // 接受到发送信号，进入发送状态
                         end
  4'b0100: if(BaudTick) begin
                            state <= 4'b1000;  // 发送开始位 - 0电平
                  TxD <= 1'b0;
                            end
  4'b1000: if(BaudTick) begin
                            state <= 4'b1001;  // bit 0
                  TxD <= TxD_dataReg[0];
                            end
  4'b1001: if(BaudTick) begin
                            state <= 4'b1010;  // bit 1
                  TxD <= TxD_dataReg[1];
                        end
  4'b1010: if(BaudTick) begin
                            state <= 4'b1011;  // bit 2
                  TxD <= TxD_dataReg[2];
                            end
  4'b1011: if(BaudTick) begin
                            state <= 4'b1100;  // bit 3
                  TxD <= TxD_dataReg[3];
                            end
  4'b1100: if(BaudTick) begin
                            state <= 4'b1101;  // bit 4
                  TxD <= TxD_dataReg[4];
                            end
  4'b1101: if(BaudTick) begin
                            state <= 4'b1110;  // bit 5
                  TxD <= TxD_dataReg[5];
                            end
  4'b1110: if(BaudTick) begin
                            state <= 4'b1111;  // bit 6
                  TxD <= TxD_dataReg[6];
                            end
  4'b1111: if(BaudTick) begin
                            state <= 4'b0010;  // bit 7
                  TxD <= TxD_dataReg[7];
                            end
  4'b0010: if(BaudTick) begin
                            state <= 4'b0011;  // stop1
                  TxD <= 1'b1;
                            end

  4'b0011: if(BaudTick) begin
                            state <= 4'b0000;  // stop2
                        TxD <= 1'b1;
                            end
  default: if(BaudTick) begin
                            state <= 4'b0000;
                TxD <= 1'b1;
              end
 endcase
endmodule

接收端：

module rcv(clk,
           rst,
           RxD,
           RxD_data,
           RxD_data_ready,
           );
input       clk,
            rst,
            RxD;
output[7:0] RxD_data;        // 接收数据寄存器        
output      RxD_data_ready;  // 接收完8位数据，RxD_data 值有效时，RxD_data_ready 输出读信号


parameter  ClkFrequency = 25000000;  // 时钟频率－25MHz
parameter  Baud = 115200;            // 波特率－115200

reg[2:0]  bit_spacing;
reg       RxD_delay;
reg      RxD_start;
reg[3:0]  state;
reg[7:0]  RxD_data;
reg       RxD_data_ready;

// 波特率产生，使用8倍过采样
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
wire    [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg     [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;

always @(posedge clk or negedge rst)
   if(~rst)
      Baud8GeneratorAcc <= 0;
   else  
    Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;

// Baud8Tick 为波特率的8倍 － 115200*8 = 921600
wire  Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth]; 

// next_bit 为波特率 － 115200
always @(posedge clk or negedge rst)
 if(~rst||(state==0))
      bit_spacing <= 0;
 else if(Baud8Tick)
    bit_spacing <= bit_spacing + 1;
wire next_bit = (bit_spacing==7);

// 检测到 TxD 有下跳沿时，RxD_start 置1，准备接收数据
always@(posedge clk)
 if(Baud8Tick)
 begin
  RxD_delay <= RxD;
    RxD_start <= (Baud8Tick & RxD_delay & (~RxD));
 end 

// 状态机接收数据
always@(posedge clk or negedge rst)
 if(~rst)
    state <= 4'b0000;
 else if(Baud8Tick)
    case(state)
     4'b0000: if(RxD_start) state <= 4'b1000;  // 检测到下跳沿
     4'b1000: if(next_bit)  state <= 4'b1001;  // bit 0
     4'b1001: if(next_bit)  state <= 4'b1010;  // bit 1
     4'b1010: if(next_bit)  state <= 4'b1011;  // bit 2
     4'b1011: if(next_bit)  state <= 4'b1100;  // bit 3
     4'b1100: if(next_bit)  state <= 4'b1101;  // bit 4
     4'b1101: if(next_bit)  state <= 4'b1110;  // bit 5
     4'b1110: if(next_bit)  state <= 4'b1111;  // bit 6
     4'b1111: if(next_bit)  state <= 4'b0001;  // bit 7
     4'b0001: if(next_bit)  state <= 4'b0000;  // 停止位
     default: state <= 4'b0000;
    endcase

// 保存接收数据到 RxD_data 中
always @(posedge clk or negedge rst)
   if(~rst)
      RxD_data <= 8'b00000000;
 else if(Baud8Tick && next_bit && state[3])
  RxD_data <= {RxD, RxD_data[7:1]};

// RxD_data_ready 置位信号
always @(posedge clk or negedge rst)
   if(~rst)
      RxD_data_ready <= 0;
 else
    RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001);

endmodule

 

为了测试收发是否正常，写的Test Bench

`timescale 1ns / 1ns
module rs232_test;
 reg       clk,
      rst,
      TxD_start;
 reg [7:0]  TxD_data; 
 wire[7:0]  RxD_data; 
 wire     //RxD,
      TxD,
      TxD_busy,
      RxD_data_ready;
     
trans trans(.clk(clk),
            .rst(rst),
      .TxD_start(TxD_start),
      .TxD_busy(TxD_busy),
      .TxD_data(TxD_data),
      .TxD(TxD)
    );
    
rcv rcv(.clk(clk),
        .rst(rst),
        .RxD(TxD),     // 收发相接时 RxD = TxD
        .RxD_data(RxD_data),
        .RxD_data_ready(RxD_data_ready)
   );   
   
initial begin
 TxD_start = 0;
   TxD_data = 0; 
   clk = 0;
   rst = 1;
   #54 rst = 0;
   #70 rst = 1;
   #40 TxD_start = 1'b1;
   #10 TxD_data = 8'b11011001;
   #100 TxD_start = 1'b0;
end   

always begin
      #30 clk = ~clk;
      #10 clk = ~clk;     
  end
endmodule