em78p372n.inc

义隆EM78P372N资料

;******************************************************;
;  Tilte:       EM78P372N include file                 ;
;  Description: The Definition of EM78P372N Registers  ;
;  Company:     ELAN MICROELECTRONICS (SZ) LTD.        ;
;  Date:        2010/07/25                             ;
;******************************************************;
;
;======================================================;
; Operational Registers Define                         ;
;======================================================;
;
;======================================================;
; Registers R0~R3F                                     ;
;======================================================;
;
; R0/IAR: Indirect Address Register
;
R0		==	0X00:rpage 0
;
; R1/TCC: Time Clock/Counter
;
R1		==	0X01:rpage 0
TCC		==	0X01:rpage 0
RTCC    ==	0x01:rpage 0
;
;
; R2/PC: Program Counter & Stack
;
R2		==	0X02:rpage 0
PC		==	0X02:rpage 0
;
;
; R3/PSR: Process Status Register
;
R3		==	0X03:rpage 0
STATUS	==	0X03:rpage 0
;
	;{
	    C	  	==  STATUS.0
	    DC	 	==  STATUS.1
	    Z	  	==  STATUS.2
	    P	  	==  STATUS.3
	    T	  	==  STATUS.4
	    
	    IOCS  	==  STATUS.6 ; I/O REGISTER PEGER CONTER BIT
	    RST	  	==  STATUS.7
	;}		
;                          
; RAM Select Register (RSR)
;
  R4	==	0X4:rpage 0
  RSR	==	0X4:rpage 0
  		S_BANK	==	 RSR.7
;
; R5(Port 5 data Register)
;
R5		==	0X5:rpage 0
PORT5	==	0X5:rpage 0
;
; R6(Port 6 data Register)
;
R6		==	0X6:rpage 0
PORT6	==	0X6:rpage 0
;
; R7(Port 7 data Register)
;
R7		==	0X7:rpage 0
PORT7	==	0X7:rpage 0
;
; R8 (AISR: ADC Input Select Register)
;
R8		==	0X08:rpage 0
AISR	==	0X08:rpage 0		     ;ADC INPUT SELECT REGISTER
		ADE0	==	AISR.0		     ;0/1 DISABLE/ENABLE P50 AS AD INPUT PIN
		ADE1	==	AISR.1		     ;0/1 DISABLE/ENABLE P51 AS AD INPUT PIN
		ADE2	==	AISR.2		     ;0/1 DISABLE/ENABLE P52 AS AD INPUT PIN
		ADE3	==	AISR.3		     ;0/1 DISABLE/ENABLE P53 AS AD INPUT PIN
    	ADE4    ==	AISR.4           ;0/1 DISABLE/ENABLE P67 AS AD INPUT PIN
        ADE5    ==	AISR.5           ;0/1 DISABLE/ENABLE P70 AS AD INPUT PIN
        ADE6    ==	AISR.6           ;0/1 DISABLE/ENABLE P55 AS AD INPUT PIN
        ADE7    ==	AISR.7           ;0/1 DISABLE/ENABLE P57 AS AD INPUT PIN
;
; R9 (ADCON: ADC Control Register)
;
R9		==	0X09:rpage 0
ADCON	==	0X09:rpage 0
		ADIS0	==	ADCON.0			;Bit 2 ~ Bit 0 (ADIS2 ~ADIS0): Analog Input Select
		ADIS1	==	ADCON.1
        ADIS2   ==	ADCON.2
		ADPD	==	ADCON.3			;ADC POWER DOWEN MODE
		ADRUN	==	ADCON.4			;ADC starts to RUN
		CKR0	==	ADCON.5			;Bit 5 ~ Bit 6 The prescaler of ADC oscillator clock rate
		CKR1	==	ADCON.6			;
		VREFS	==	ADCON.7			;THE INPUT SOURCE OF THE VREF OF THE ADC
;
; RA (ADOC: ADC Offset Calibration Register)
;
RA		==	0X0A:rpage 0
ADOC	==	0X0A:rpage 0
		VOF0	==	ADOC.3
		VOF1	==	ADOC.4
		VOF2	==	ADOC.5
		SIGN	==	ADOC.6
		CALI	==	ADOC.7
	 ;{
	 ;|------|-------|-------|----------|------|;
	 ;|VOF[2]|VOF[1] |VOF[0] |EM78P372N |ICE341|;
	 ;|------|-------|-------|----------|------|;
	 ;|0	 |0	 |0	 |0LSB	    |0LSB  |;
	 ;|------|-------|-------|----------|------|;        
	 ;|0	 |0	 |1	 |2LSB	    |2LSB  |;
	 ;|------|-------|-------|----------|------|;      
	 ;|0	 |1	 |0	 |4LSB	    |4LSB  |;
	 ;|------|-------|-------|----------|------|;      
	 ;|0	 |1	 |1	 |6LSB	    |6LSB  |;
	 ;|------|-------|-------|----------|------|;      
	 ;|1	 |0	 |0	 |8LSB	    |8LSB  |;
	 ;|------|-------|-------|----------|------|;      
	 ;|1	 |0	 |1	 |10LSB	    |10LSB |;
	 ;|------|-------|-------|----------|------|;      
	 ;|1	 |1	 |0	 |12LSB	    |12LSB |;
	 ;|------|-------|-------|----------|------|;      
	 ;|1	 |1	 |1	 |14LSB	    |14LSB |;
	 ;|------|-------|-------|----------|------|;      
	 ;}	 
;
; RB (ADDATA: Converted Value of ADC) 
;       
RB		==	0X0B:rpage 0		;AD DATA HIGH 8 BIT
ADDATA	==	0X0B:rpage 0
;
; RC (ADDATA1H: Converted Value of ADC)
;        
RC		==	0X0C:rpage 0
ADDATA1H==	0X0C:rpage 0		;AD DATA HIGHT 4 BIT
;
; RD (ADDATA1L: Converted Value of ADC)
;        
RD		==	0X0D:rpage 0		;AD DATA LOW 8 BIT
ADDATA1L==	0X0D:rpage 0		
;
; RE (Interrupt Status 1 and Wake-up Control Register)
;
RE		==	0X0E:rpage 0		;INTERRUPT STATUS & WAKE UP CONTROL REGISTER
ISR1    ==  0X0E:rpage 0
WUCR    ==  0X0E:rpage 0
        LVDWE   ==	WUCR.0
		ICWE	==	WUCR.1
		CMPWE	==	WUCR.2
		ADWE	==	WUCR.3
		CMPIF	==	ISR1.4
		ADIF	==	ISR1.5
        LVDIF   ==	ISR1.6
        LVD     ==	ISR1.7
;
; RF (Interrupt Status 2 Register)
;
RF		==	0X0F:rpage 0		;INTERRUPT STATUS REGISTER
ISR2    ==	0X0F:rpage 0
		TCIF	==	ISR2.0
		ICIF	==	ISR2.1
		EXIF	==	ISR2.2
		PWM1IF	==	ISR2.3
		PWM2IF	==	ISR2.4
		DT1IF	==	ISR2.5
		DT2IF	==	ISR2.6
;BANK1
TBHP	==	0X05:rpgae 1		;Table point register for instruction TBRD
		RBIT8	==	TBHP.0
		RBIT9	==	TBHP.1
		RBIT10	==	TBHP.2	
		MLB		==	TBHP.7
TBLP	==	0X06:rpgae 1		;Table Point register for instruction TBRD
		RBIT0	==	TBLP.0
		RBIT1	==	TBLP.1
		RBIT2	==	TBLP.2
		RBIT3	==	TBLP.3
		RBIT4	==	TBLP.4
		RBIT5	==	TBLP.5
		RBIT6	==	TBLP.6	
		RBIT7	==	TBLP.7
PWMCON	==	0x7:rpage 1			;PWM Control register
		PWM1E	==	PWMCON.0
		PWM2E	==	PWMCON.1
		PWMCAS	==	PWMCON.2
TMRCON	==	0X08:rpage 1		;Timer Control register
		T1P0	==	TMRCON.0	
		T1P1	==	TMRCON.1
		T1P2	==	TMRCON.2
		T2P0	==	TMRCON.3
		T2P1	==	TMRCON.4
		T2P2	==	TMRCON.5
		T1EN	==	TMRCON.6
		T2EN	==	TMRCON.7	
PRD1	==	0X09:rpage 1		;PWM1 Time period
PRD2	==	0X0A:rpage 1		;PWM2 Time Period
DT1		==	0X0B:rpage 1		;PWM1 Duty Cycle
DT2		==	0X0C:rpage 1		;PWM2 Duty Cycle	
LVDIWR	==	0X0E:rpage 1		;LVD Interrupt and wake up register
		EXWE	==	LVDIWR.0
		LVD0	==	LVDIWR.4
		LVD1	==	LVDIWR.5
		LVDEN	==	LVDIWR.6
		LVDIE	==	LVDIWR.7
SCR		==	0X0F:rpage 1
		RCM0	==	SCR.0		;IRC mode select 
		RCM1	==	SCR.1
		SHS0	==	SCR.2		
		SHS1	==	SCR.3		;
		
		IDLE	==	SCR.4		;Idle mode enable bit
		CPUS	==	SCR.5		;CPU Oscillator source select
		TIMERSC	==	SCR.6		;TCC,PWM1,PWM2 clock source select
		
;
;
;======================================================;
; Special Purpose Registers Define                     ;
;======================================================;
;
; A: Accumulator
; It can't be addressed.
;
;
; CONT: Control Register
;
        ;{
            INTE   ==  7    ; INT signal edge
                               ; 0: Interrupt occurs at the rising edge on the INT pin
                               ; 1: Interrupt occurs at the falling edge on the INT pin
            _INT    ==  6    ; Interrupt enable
                               ; 0: Masked by DISI or hardware interrupt
                               ; 1: Enabled by ENI/RETI instructions
            TS     ==  5     ; TCC signal source
                               ; 0: Internal instruction cycle clock
                               ; 1: Transition on TCC pin
            TE     ==  4     ; TCC signal edge
                               ; 0: Increment if the transition from low to high takes place on TCC pin
                               ; 1: Increment if the transition from high to low takes place on TCC pin
            PSTE   ==  3     ; Prescaler enable bit for TCC
            		       ;0 = prescaler disable bit. TCC rate is 1:1.
            		       ;1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.
            PSR2   ==  2     ;
            PSR1   ==  1     ;
            PSR0   ==  0     ; (PSR2~PSR0): TCC prescaler Select bits
                                ; ------|------|-------|----------- ;
                                ; PSR2  |PSR1  |PSR0   | TCC Rate   ;
                                ;-------|------|-------|------------;
                                ;   0   |  0   |  0    |   1:2      ;
                                ;-------|------|-------|------------;
                                ;   0   |  0   |  1    |   1:4      ;
                                ;-------|------|-------|------------;
                                ;   0   |  1   |  0    |   1:8      ;
                                ;-------|------|-------|------------;
                                ;   0   |  1   |  1    |   1:16     ;
                                ;-------|------|-------|------------;
                                ;   1   |  0   |  0    |   1:32     ;
                                ;-------|------|-------|------------;
                                ;   1   |  0   |  1    |   1:64     ;
                                ;-------|------|-------|------------;
                                ;   1   |  1   |  0    |   1:128    ;
                                ;-------|------|-------|------------;
                                ;   1   |  1   |  1    |   1:256    ;
                                ; ------|------|-------|----------- ;
        ;}
;
        ;{
            ; PSR0 ~ PSR2
;
            TCCRate2    == 0x00
            TCCRate4    == 0x01
            TCCRate8    == 0x02
            TCCRate16   == 0x03
            TCCRate32   == 0x04
            TCCRate64   == 0x05
            TCCRate128  == 0x06
            TCCRate256  == 0x07
        ;}
;
;
;
; IOC50 ~ IOC70 (I/O Port Control Register)
;
IOC50	==	0X05:iopage 0
P5CR    ==	0X05:iopage 0
IOC60	==	0X06:iopage 0
P6CR	==	0X06:iopage 0
IOC70	==	0X07:iopage 0
P7CR	==	0X07:iopage 0
;
; IOC80 (Comparator Control Register)
;
IOC80	==	0X08:iopage 0
CCR		==	0X08:iopage 0
CMPCR	==	0X08:iopage 0
		COS0	==	3
		COS1	==	4
		CMPOUT	==	5
		
;
; IOC90 (TCCB and TCCC Control Register)
;
IOC90	==	0X09:iopage 0			;TCCB AND TCCC CONTORL REGISTER
TMR1	==	0X09:iopage 0
;
; IOCA0 (IR and TCCC Scale Control Register)
IOCA0	==	0X0A:iopage 0
TMR2	==	0X0A:iopage 0

;
; IOCB0 (Pull-down Control Register)
;
IOCB0	==	0X0B:iopage 0		;PULL DOWN CONTROL REGISTER
PDCR	==	0X0B:iopage 0
P5PDCR	==	0x0B:iopage 0
	PD50	==0
	PD51	==1
    PD52	==2
    PD53	==3
    PD54	==4
    PD55	==5
    PD56	==6
	PD57	==7
;
; IOCC0 (Open-drain Control Register)
;
IOCC0	==	0X0C:iopage 0		;OPEN DRAIN CONTROL REGISTER
ODCR	==	0X0C:iopage 0
P6ODCR  ==  0X0C:iopage 0
	OD60	==0
	OD61	==1
	OD62	==2
	OD63	==3
	OD64	==4
	OD65	==5
	OD66	==6
	OD67	==7
;
; IOCD0 (Pull-high Control Register)
;
IOCD0	==	0X0D:iopage 0		;PULL HIGH CONTROL REGISTER
PHCR1	==	0X0D:iopage 0
P5PHCR	==	0X0D:iopage 0
	PH50	==0
	PH51	==1
	PH52	==2
	PH53	==7
	PH54	==4
	PH55	==5
	PH56	==6
	PH57	==7
;
; IOCE0 (WDT Control Register and Interrupt Mask Register 2)
;
IOCE0	==	0X0E:iopage 0		;WDT CONTROL REGISTER
WDTCR	==	0X0E:iopage 0
IMR2	==	0X0E:iopage 0
		PSW0	==	0
		PSW1	==	1
		PSW2	==	2			;WDT PRESCALER BITS
		PSWE	==	3			;
		CMPIE	==	4			;CMPIF INTERRUPT ENABLE BIT
		ADIE	==	5			;ADIF INTERRUPT ENABLE BIT
		EIS     ==	6			;
		WDTE	==	7			;0/1 DISABLE/ENABLE WDT
;
; IOCF0 (Interrupt Mask Register)
;
IOCF0	==	0X0F:iopage 0
IMR		==	0X0F:iopage 0
        TCIE    ==	0
        ICIE    ==	1
        EXIE    ==	2
        PWM1IE  ==	3
        PWM2IE  ==	4
        DT1IE  ==	5
        DT2IE  ==	6
       

;
;I/0 REGISTER PAGE 1
;IOC51	High sink control register1
IOC51	==	0X05:iopage 1		;High sink control register
HSCR1	==	0X05:iopage 1
P5HSCR 	==	0x05:iopage 1
;IOC61	High sink control register2
IOC61	==	0X06:iopage 1
HSCR2	==	0x06:iopage 1
P6HSCR	==	0x06:iopage 1
;IOC71	High driver control registet1
IOC71	==	0X07:iopage 1		;HIgh Driver control register1
HDCR1	==	0X07:iopage 1
P5HDCR	==	0X07:iopage 1
;IOC81	High driver control registet2
IOC81	==	0X08:iopage 1
HDCR2	==	0X08:iopage 1
P6HDCR	==	0X08:iopage 1
;IOCF1	pull high control register
IOCF1	==	0X0F:iopage 1
PHCR2	==	0X0F:iopage 1
P6PHCR	==	0X0F:iopage 1
;

;----------------------------
;********************************************************;
;CLEAR EM78P372N GENERAL REGISTER MACRO PROGRAM           ;
;                                                        ;
;********************************************************;
;
 M372NCLRRAMBANK  MACRO 
;
     MOV   	A,@0X10
     MOV   	RSR,A
$_CLRLOOP: 	   
     CLR   	R0   
     INC   	RSR
     JBC   	RSR,6
     BS    	RSR,5 
     MOV	A,RSR
     AND    	A,@0X7F
     JBS	STATUS,Z        
     JMP   	$_CLRLOOP 
;     
     ENDM