vecter.c

freesacle的实时操作系统UCOS的开发程序

/********************************************************************
*
* 文件名： Vector.c
*
* 说明:
*       中断向量和中断服务程序的入口
*
***************************************************************************
*/
/*-----------------------------------------------------------------------
*(1)中断服务函数的列表：
*
* 
*/
extern void near _Startup(void);      //  Startup routine 
extern void near OSTickISR(void);
extern void near PAover_Int(void);
extern void near IOC_Int(void);
extern void near SCI_Int(void);
extern void near ATD0_Int(void);
extern void near ATD1_Int(void); 
extern void near IRQ_Int (void);

#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
__interrupt void UnimplementedISR(void)
{
   /* Unimplemented ISRs trap.*/
   asm BGND;
}
/*--------------------------------------------------------------------------
* (2)中断向量表：
*
*/
typedef void (*near tIsrFunc)(void);
const tIsrFunc _vect[] @0xEF80 = {     /* Interrupt table */
        UnimplementedISR,        // vector 63 
        UnimplementedISR,        // vector 62 
        UnimplementedISR,        // vector 61 
        UnimplementedISR,        // vector 60 
        UnimplementedISR,        // vector 59 
        UnimplementedISR,        // vector 58 
        UnimplementedISR,        // vector 57 PWM Emergency Shutdown
        UnimplementedISR,        // vector 56 Port P Interrupt
        UnimplementedISR,        // vector 55 MSCAN 4 transmit
        UnimplementedISR,        // vector 54 MSCAN 4 receive
        UnimplementedISR,        // vector 53 MSCAN 4 errors
        UnimplementedISR,        // vector 52 MSCAN 4 wake-up
        UnimplementedISR,        // vector 51 MSCAN 3 transmit
        UnimplementedISR,        // vector 50 MSCAN 3 receive
        UnimplementedISR,        // vector 49 MSCAN 3 errors
        UnimplementedISR,        // vector 48 MSCAN 3 wake-up
        UnimplementedISR,        // vector 47 MSCAN 2 transmit
        UnimplementedISR,        // vector 46 MSCAN 2 receive
        UnimplementedISR,        // vector 45 MSCAN 2 errors
        UnimplementedISR,        // vector 44 MSCAN 2 wake-up
        UnimplementedISR,        // vector 43 MSCAN 1 transmit
        UnimplementedISR,        // vector 42 MSCAN 1 receive
        UnimplementedISR,        // vector 41 MSCAN 1 errors
        UnimplementedISR,        // vector 40 MSCAN 1 wake-up
        UnimplementedISR,        // vector 39 MSCAN 0 transmit
        UnimplementedISR,        // vector 38 MSCAN 0 receive
        UnimplementedISR,        // vector 37 MSCAN 0 errors
        UnimplementedISR,        // vector 36 MSCAN 0 wake-up
        UnimplementedISR,        // vector 35 Flash
        UnimplementedISR,        // vector 34 EEPROM
        UnimplementedISR,        // vector 33 SPI2
        UnimplementedISR,        // vector 32 SPI1
        UnimplementedISR,        // vector 31 IIC Bus
        UnimplementedISR,        // vector 30 DLC
        UnimplementedISR,        // vector 29 SCME
        UnimplementedISR,        // vector 28 CRG lock
        UnimplementedISR,        // vector 27 Pulse Accumulator B Overflow
        OSTickISR,               // vector 26 Modulus Down Counter underflow
        UnimplementedISR,        // vector 25 Port H
        UnimplementedISR,        // vector 24 Port J
        ATD1_Int,                // vector 23 ATD 1 
        ATD0_Int,                // vector 22 ATD 0 
        UnimplementedISR,        // vector 21 SCI 1 
        SCI_Int,                  // vector 20 SCI 0 
        UnimplementedISR,        // vector 19 SPI0  
        UnimplementedISR,        // vector 18 Pulse accumulator input edge
        PAover_Int,              // vector 17 Pulse accumulator A overflow
        UnimplementedISR,        // vector 16 Time Overflow 
        UnimplementedISR,        // vector 15 Timer channel 7
        UnimplementedISR,        // vector 14 Timer channel 6
        UnimplementedISR,        // vector 13 Timer channel 5
        UnimplementedISR,        // vector 12 Timer channel 4
        UnimplementedISR,        // vector 11 Timer channel 3
        UnimplementedISR,        // vector 10 Timer channel 2
        UnimplementedISR,        // vector 09 Timer channel 1
        IOC_Int,                  // vector 08 Timer channel 0        
        UnimplementedISR,        // vector 07 Real Time Interrupt
        IRQ_Int,                 // vector 06 IRQ
        UnimplementedISR,        // vector 05 XIRQ
        UnimplementedISR,        // vector 04 SWI
        UnimplementedISR,        // vector 03 VTRA
        UnimplementedISR,        // vector 02 COP Failure Reset
        UnimplementedISR,        // vector 01 Clock Monitor Fail Reset/
        _Startup                 // vector 00 Reset vector 
   };