da8.vhd

TLV5628 8位da的vhdl控制程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity da8 is 
port (
      reset: in std_logic;
	clk:in std_logic;
    data:out std_logic;
	clkda:out std_logic;
address:out std_logic_vector(7 downto 0);
datain:in std_logic_vector(7 downto 0);
--romclk:out std_logic;
    load:out std_logic


);
end  da8;
architecture behave of da8 is
signal  configcounter: std_logic_vector(3 downto 0);
signal chn: std_logic_vector(2 downto 0);
signal counter0,adda,addb,addc,dadd: std_logic_vector(7 downto 0);
signal counter1: std_logic_vector(7 downto 0);
signal datacounter: std_logic_vector(7 downto 0);
signal chnclk,clko,clk1,clk2: std_logic;

 begin
--romclk<=chnclk; 
clkda<=clko;
address<=add;

counterpro:process(reset,clk)
 begin 
 if reset='1' then
counter0<=x"00";
 elsif  clk'event and clk='1' then
 if counter0=x"13" then
 counter0<=x"00"; 
 else 
 counter0<=counter0+1;
 end if;
 end if;
 end process;



clk1pro:process(reset,clk,counter0)
 begin 
 if reset='1' then 
clk1<='0';
 elsif  clk'event and clk='1' then
 if counter0>=x"00"and counter0<=x"0a" then
clk1<='1';
 else 
clk1<='0';
 end if;
 end if;
 end process;



datacounterpro:process(reset,clk1)
begin
if reset='1' then
datacounter<=x"00";
elsif clk1'event and clk1='1' then
if datacounter=x"20" then
datacounter<=x"00";
else 
datacounter<=datacounter+1;
end if;
end if;
end process;

clkopro:process(reset,clk1,datacounter)
begin
if reset='1' then
clko<='0';
elsif datacounter>=x"00" and  datacounter<=x"0b" then
clko<=clk1;
else
clko<='0';
end if;

end process;
chnclk:process(reset,clk1)
begin
if reset='1' then
chnclk<='0';
elsif clk1'event and clk1='1' then
if datacounter>=x"00" and datacounter<=x"0f"  then 
chnclk<='1';
else
chnclk<='0';
end if;
end if;
end process;


chnpro:process(reset,chnclk)
begin
if reset='1' then
chn<="000";
elsif chnclk'event and chnclk='1' then
chn<=chn+1;
end if;
end process;

addclkro:process(reset,chnclk)
begin
if reset='1' then
addclk<='0';
elsif chnclk'event and chnclk='1' then
if chn>="000" and chn<="011" then
addclk='1';
elsif addclk='0'; 
end if;
end process;

addaprO:process(reset,addclk)

begin
if reset='1' then
adda<=x"00";
elsif addclk'event and addclk='1' then
adda<=adda+1;
end if;
end process;

addbprO:process(reset,addclk)

begin
if reset='1' then
addb<=x"55";
elsif addclk'event and addclk='1' then
addb<=addb+1;
end if;
end process;

addprO:process(reset,addclk)

begin
if reset='1' then
addc<=x"aa";
elsif addclk'event and addclk='1' then
addc<=addc+1;
end if;
end process;

datapro:process(chn,dadd,datacounter)
begin
 case datacounter is
when x"00"=>
data<=chn(2);
--data<='0';
when x"01"=>
data<=chn(1);
--data<='0';
when x"02"=>
data<=chn(0);
--data<='0';
when x"03"=>
data<='0';
when x"04"=>
data<=dadd(7);
when x"05"=>
data<=dadd(6);
when x"06"=>
data<=dadd(5);
when x"07"=>
data<=dadd(4);
when x"08"=>
data<=dadd(3);
when x"09"=>
data<=dadd(2);
when x"0a"=>
data<=dadd(1);
when x"0b"=>
data<=dadd(0);
when others=>
data<='0';
end case;
end process;

--datapro:process(datacounter)
--begin
 --case datacounter is
--when x"05"=>
--data<='1';
--when x"00"=>
--data<='1';
--when x"01"=>
--data<='1';
--when others=>
--data<='0';
--end case;

--end process;


loadpro:process(reset,datacounter)
begin
if reset='1' then
load<='1';
elsif  datacounter>=x"0c" and datacounter>=x"1f"  then
load<='0';
else
load<='1';
end if;
--end if;
end process;

daddpro:process(reset,datain,datacounter)
begin
if reset='1' then
dadd<=x"00";
elsif  
datacounter>=x"0c"  then
add<=adda;

end if;
--end if;
end process;
end   behave ;

addprocess:process(


daddpro:process(reset,datain,datacounter)
begin
if reset='1' then
dadd<=x"00";
elsif  datacounter>=x"0c" and datacounter>=x"1f"  then
dadd<=datain;
end if;
--end if;
end process;
end   behave ;