ledctrl.vhd

利用74ls164控制数码管的vhdl程序

--利用74ls164控制数码管，采用A与时钟两个信号共同控制，

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 

entity ledctrl is
port(
reset:in std_logic;
clk:in std_logic;
a:out std_logic;
clko:out std_logic;
clr:out std_logic); 
end ledctrl;
architecture behavior of ledctrl is

signal counter2,counter3,counter4:std_logic_vector(15 downto 0);
signal counter:std_logic_vector(11 downto 0);
signal counter5:std_logic_vector(2 downto 0);
signal data:std_logic_vector(7 downto 0);
signal clr1,clk2,clk1,clk3,clk0:std_logic;

begin


datapro:process(counter5)
begin
case counter5 is
when "000"=>data<="10000000";
when "001"=>data<="11111001";
when "010"=>data<="10100100";
when "011"=>data<="10110000";
when "100"=>data<="10011001";
when "101"=>data<="10010010";
when "110"=>data<="10000010";
when "111"=>data<="11111000";
end case;
end  process;

counterpro:process(reset,clk)
begin 
if reset='1' then
counter<=x"000"; 
elsif  clk'event and clk='1' then
if counter=x"400" then
counter<=x"000";
else
counter<=counter+1;
end if; 
end if;
end process;

counterpro:process(reset,clk,counter)
begin 
if reset='1' then
clk0<='0'; 
elsif  clk'event and clk='1' then
if counter>=x"000" and counter<=x"200" then
clk0<='1'; 
else
clk0<='0'; 
end if; 
end if;
end process;

clk2pro:process(reset,clk,counter)
begin 
if reset='1' then
clk2<='0'; 
elsif  clk'event and clk='1' then
if counter>=x"180" and counter<=x"380" then
clk2<='1'; 
else
clk2<='0'; 
end if;
end if;
 end process;

counterpro:process(reset,clk,counter)
begin 
if reset='1' then
clk1<='0'; 
elsif  clk'event and clk='1' then
if counter>=x"100" and counter<=x"300" then
clk1<='1'; 
else
clk1<='0'; 
end if; 
end if;
 end process;

counterpro:process(reset,clk0)
 begin 
if reset='1' then
counter2<=x"0000"; 
elsif  clk0'event and clk0='1' then
if counter2=x"4000" then 
counter2<=x"0000";
else 
counter2<=counter2+1;
end if;
end if; 
end process;

counterpro:process(reset,clk2)
 begin 
if reset='1' then
counter4<=x"0000"; 
elsif  clk2'event and clk2='1' then
if counter4=x"4000" then 
counter4<=x"0000";
else 
counter4<=counter4+1;
end if;
end if; 
 end process;


clk4pro:process(reset,clk1,counter3)
 begin 
if reset='1' then
clk3<='0'; 
elsif  clk1'event and clk1='1' then
if counter3=x"3000" then
clk3<='1';
else 
clk3<='0';
end if;
end if; 
end process;

 counter4pro:process(reset,clk3)
 begin
if reset='1' then
counter5<="000"; 
elsif  clk3'event and clk3='1' then
if counter5="111" then 
counter5<="000";
else 
counter5<=counter5+1;
end if;
end if; 
 end process;

counterpro:process(reset,clk1)
begin 
if reset='1' then
counter3<=x"0000"; 
elsif  clk1'event and clk1='1' then
if counter3=x"4000" then 
counter3<=x"0000";
else 
counter3<=counter3+1;
end if;
end if; 
 end process;


clkopro:process(clk1,counter3)
 begin 
if counter3>=x"000"  and  counter3<=x"03f" then
clko<=clk1;
else
clko<='0'; 
end if;
end process;


 apro:process(data,counter2)
 begin
case counter2 is
when x"0000"=>a<=data(7);
when x"0001"=>a<=data(6);
when x"0002"=>a<=data(5);
when x"0003"=>a<=data(4);
when x"0004"=>a<=data(3);
when x"0005"=>a<=data(2);
when x"0006"=>a<=data(1);
when x"0007"=>a<=data(0);--"按照时序"

when x"000d"=>a<='0';--"1"
when x"000e"=>a<='0';

when x"0011"=>a<='0';--"2"
when x"0013"=>a<='0';
when x"0014"=>a<='0';
when x"0016"=>a<='0';
when x"0017"=>a<='0';

when x"0019"=>a<='0';--"3"
when x"001c"=>a<='0';
when x"001d"=>a<='0';
when x"001e"=>a<='0';
when x"001f"=>a<='0';

when x"0021"=>a<='0';--"4"
when x"0022"=>a<='0';
when x"0025"=>a<='0';
when x"0026"=>a<='0';

when x"0029"=>a<='0';--"5"
when x"002a"=>a<='0';
when x"002c"=>a<='0';
when x"002d"=>a<='0';
when x"002f"=>a<='0';

when x"0031"=>a<='0';--"6"
when x"0032"=>a<='0';
when x"0033"=>a<='0';
when x"0034"=>a<='0';
when x"0035"=>a<='0';
when x"0037"=>a<='0';

when x"003d"=>a<='0';--"7"
when x"003e"=>a<='0';
when x"003f"=>a<='0';

when others=>a<='1';

end case;
end process;

end behavior;