📄 七段数码管 .txt
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PORT ( disdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sel: IN STD_LOGIC;
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ;
ARCHITECTURE behav OF DECL7S IS
signal led_temp: std_logic_vector(3 downto 0);
BEGIN
PROCESS( disdata )
BEGIN
if(sel='1')
then led_temp<=disdata(7 downto 4);
else led_temp<=disdata(3 downto 0);
end if;
CASE led_temp IS
WHEN "0000" => LED7S <= "0111111" ;
WHEN "0001" => LED7S <= "0000110" ;
WHEN "0010" => LED7S <= "1011011" ;
WHEN "0011" => LED7S <= "1001111" ;
WHEN "0100" => LED7S <= "1100110" ;
WHEN "0101" => LED7S <= "1101101" ;
WHEN "0110" => LED7S <= "1111101" ;
WHEN "0111" => LED7S <= "0000111" ;
WHEN "1000" => LED7S <= "1111111" ;
WHEN "1001" => LED7S <= "1101111" ;
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS ;
END behav;
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