0809.修改.txt

这是基于VHDL的0809可编程程序

library ieee;
use ieee.std_logic_1164.all;
entity ad is
  port(d: in std_logic_vector(7 downto 0);
       clk,eoc,clk1:in std_logic;
       ale,start,oe: out std_logic;
       led7s:out std_logic_vector(6 downto 0);
       sel:out std_logic);
end ad;
architecture behav of ad is
   type states is (st0,st1,st2,st3,st4);
        signal current_state,next_state:states :=st0;
        signal regl :std_logic_vector(7 downto 0);
        signal lock :std_logic;
        signal led_temp:std_logic_vector(3 downto 0);
begin
com:process(current_state,eoc)    
   begin
        case current_state is
             when st0=>ale<='0';start<='0';lock<='0';oe<='0';
                  next_state<=st1;
             when st1=>ale<='1';start<='1';lock<='0';oe<='0';
                  next_state<=st2;
             when st2=>ale<='0';start<='0';lock<='0';oe<='0';
                  if (eoc='1') then next_state<=st3;
                        else next_state<=st2;
                  end if;
             when st3=>ale<='0';start<='0';lock<='0';oe<='1';
                  next_state<=st4;
             when st4=>ale<='0';start<='0';lock<='1';oe<='1';
                  next_state<=st0;
         end case;
    end process com;
reg:process(clk)                                
    begin 
         if (clk'event and clk='1') then current_state<=next_state;  
         end if;
    end process reg;
latch1:process (lock)
    begin 
         if lock='1' and lock'event   then  regl<=d;
         end if ;
    end process latch1;
com1:process( regl)
     begin
         if clk1='0' then sel<='1';
            led_temp<= regl(3 downto 0);
                   case led_temp is 
                             when "0000"=>led7s<="0111111";
                             when "0001"=>led7s<="0000110";
                             when "0010"=>led7s<="1011011";
                             when "0011"=>led7s<="1001111";
                             when "0100"=>led7s<="1100110";
                             when "0101"=>led7s<="1101101";
                             when "0110"=>led7s<="1111101";
                             when "0111"=>led7s<="0000111";
                             when "1000"=>led7s<="1111111";
                             when "1001"=>led7s<="1101111";
                             when "1010"=> led7s<="1110111";
                             when "1011"=> led7s<="1111100";
                             when "1100"=> led7s<="0111001";
                             when "1101"=> led7s<="1011110";
                             when "1110"=> led7s<="1111001";
                             when "1111"=> led7s<="1110001";
                             when others=>null;
                    end case;
            else sel<='0';
                 led_temp<= regl(7 downto 4);
                      case led_temp is 
                             when "0000"=>led7s<="0111111";
                             when "0001"=>led7s<="0000110";
                             when "0010"=>led7s<="1011011";
                             when "0011"=>led7s<="1001111";
                             when "0100"=>led7s<="1100110";
                             when "0101"=>led7s<="1101101";
                             when "0110"=>led7s<="1111101";
                             when "0111"=>led7s<="0000111";
                             when "1000"=>led7s<="1111111";
                             when "1001"=>led7s<="1101111";
                             when "1010"=> led7s<="1110111";
                             when "1011"=> led7s<="1111100";
                             when "1100"=> led7s<="0111001";
                             when "1101"=> led7s<="1011110";
                             when "1110"=> led7s<="1111001";
                             when "1111"=> led7s<="1110001";
                             when others=>null;
                    end case;
           end if;
end process com1;
end behav;