📄 iolpc23xx.h
字号:
__REG32 EP24 : 1;
__REG32 EP25 : 1;
__REG32 EP26 : 1;
__REG32 EP27 : 1;
__REG32 EP28 : 1;
__REG32 EP29 : 1;
__REG32 EP30 : 1;
__REG32 EP31 : 1;
} __newdddiv_bits;
/* HcRevision Register */
typedef struct {
__REG32 REV : 8;
__REG32 :24;
} __HcRevision_bits;
/* HcControl Register */
typedef struct {
__REG32 CBSR : 2;
__REG32 PLE : 1;
__REG32 IE : 1;
__REG32 CLE : 1;
__REG32 BLE : 1;
__REG32 HCFS : 2;
__REG32 IR : 1;
__REG32 RWC : 1;
__REG32 RWE : 1;
__REG32 :21;
} __HcControl_bits;
/* HcCommandStatus Register */
typedef struct {
__REG32 HCR : 1;
__REG32 CLF : 1;
__REG32 BLF : 1;
__REG32 OCR : 1;
__REG32 :12;
__REG32 SOC : 2;
__REG32 :14;
} __HcCommandStatus_bits;
/* HcInterruptStatus Register */
typedef struct {
__REG32 SO : 1;
__REG32 WDH : 1;
__REG32 SF : 1;
__REG32 RD : 1;
__REG32 UE : 1;
__REG32 FNO : 1;
__REG32 RHSC : 1;
__REG32 :23;
__REG32 OC : 1;
__REG32 : 1;
} __HcInterruptStatus_bits;
/* HcInterruptEnable Register
HcInterruptDisable Register */
typedef struct {
__REG32 SO : 1;
__REG32 WDH : 1;
__REG32 SF : 1;
__REG32 RD : 1;
__REG32 UE : 1;
__REG32 FNO : 1;
__REG32 RHSC : 1;
__REG32 :23;
__REG32 OC : 1;
__REG32 MIE : 1;
} __HcInterruptEnable_bits;
/* HcHCCA Register */
typedef struct {
__REG32 : 8;
__REG32 HCCA :24;
} __HcHCCA_bits;
/* HcPeriodCurrentED Register */
typedef struct {
__REG32 : 4;
__REG32 PCED :28;
} __HcPeriodCurrentED_bits;
/* HcControlHeadED Registerr */
typedef struct {
__REG32 : 4;
__REG32 CHED :28;
} __HcControlHeadED_bits;
/* HcControlCurrentED Register */
typedef struct {
__REG32 : 4;
__REG32 CCED :28;
} __HcControlCurrentED_bits;
/* HcBulkHeadED Register */
typedef struct {
__REG32 : 4;
__REG32 BHED :28;
} __HcBulkHeadED_bits;
/* HcBulkCurrentED Register */
typedef struct {
__REG32 : 4;
__REG32 BCED :28;
} __HcBulkCurrentED_bits;
/* HcDoneHead Register */
typedef struct {
__REG32 : 4;
__REG32 DH :28;
} __HcDoneHead_bits;
/* HcFmInterval Register */
typedef struct {
__REG32 FI :14;
__REG32 : 2;
__REG32 FSMPS :15;
__REG32 FIT : 1;
} __HcFmInterval_bits;
/* HcFmRemaining Register */
typedef struct {
__REG32 FR :14;
__REG32 :17;
__REG32 FRT : 1;
} __HcFmRemaining_bits;
/* HcFmNumber Register */
typedef struct {
__REG32 FN :16;
__REG32 :16;
} __HcFmNumber_bits;
/* HcPeriodicStart Register */
typedef struct {
__REG32 PS :14;
__REG32 :18;
} __HcPeriodicStart_bits;
/* HcLSThreshold Register */
typedef struct {
__REG32 LST :12;
__REG32 :20;
} __HcLSThreshold_bits;
/* HcRhDescriptorA Register */
typedef struct {
__REG32 NDP : 8;
__REG32 PSM : 1; // ??
__REG32 NPS : 1; // ??
__REG32 DT : 1;
__REG32 OCPM : 1;
__REG32 NOCP : 1;
__REG32 :11;
__REG32 POTPGT : 8;
} __HcRhDescriptorA_bits;
/* HcRhDescriptorB Register */
typedef struct {
__REG32 DR :16;
__REG32 PPCM :16;
} __HcRhDescriptorB_bits;
/* HcRhStatus Register */
typedef struct {
__REG32 LPS : 1;
__REG32 OCI : 1;
__REG32 :13;
__REG32 DRWE : 1;
__REG32 LPSC : 1;
__REG32 CCIC : 1;
__REG32 :13;
__REG32 CRWE : 1;
} __HcRhStatus_bits;
/* HcRhPortStatus[1:2] Register */
typedef struct {
__REG32 CCS : 1;
__REG32 PES : 1;
__REG32 PSS : 1;
__REG32 POCI : 1;
__REG32 PRS : 1;
__REG32 : 3;
__REG32 PPS : 1;
__REG32 LSDA : 1;
__REG32 : 6;
__REG32 CSC : 1;
__REG32 PESC : 1;
__REG32 PSSC : 1;
__REG32 OCIC : 1;
__REG32 PRSC : 1;
__REG32 :11;
} __HcRhPortStatus_bits;
/* OTG_int_status Register */
typedef struct{
__REG32 timer_interrupt_status : 1;
__REG32 remove_pullup : 1;
__REG32 hnp_failure : 1;
__REG32 hnp_success : 1;
__REG32 :28;
} __OTG_int_status_bits;
/* OTG_int_enable Register */
typedef struct{
__REG32 timer_interrupt_en : 1;
__REG32 remove_pullup_en : 1;
__REG32 hnp_failure_en : 1;
__REG32 hnp_success_en : 1;
__REG32 :28;
} __OTG_int_enable_bits;
/* OTG_int_set Register */
typedef struct{
__REG32 timer_interrupt_set : 1;
__REG32 remove_pullup_set : 1;
__REG32 hnp_failure_set : 1;
__REG32 hnp_success_set : 1;
__REG32 :28;
} __OTG_int_set_bits;
/* OTG_int_clr Register */
typedef struct{
__REG32 timer_interrupt_clear : 1;
__REG32 remove_pullup_clear : 1;
__REG32 hnp_failure_clear : 1;
__REG32 hnp_success_clear : 1;
__REG32 :28;
} __OTG_int_clr_bits;
/* OTG_status and control Register */
typedef struct{
__REG32 Port_Function : 2;
__REG32 Timer_scale : 2;
__REG32 Timer_mode : 1;
__REG32 Timer_enable : 1;
__REG32 Timer_reset : 1;
__REG32 Transparent_I2C_en : 1;
__REG32 b_to_a_hnp_track : 1;
__REG32 a_to_b_hnp_track : 1;
__REG32 Pullup_removed : 1;
__REG32 : 5;
__REG32 Timer_count :16;
} __OTG_stat_ctrl_bits;
/* OTG_clock Registers
OTG_status Registers */
typedef struct{
__REG32 HOST_CLK_ON : 1;
__REG32 DEV_CLK_ON : 1;
__REG32 I2C_CLK_ON : 1;
__REG32 OTG_CLK_ON : 1;
__REG32 AHB_CLK_ON : 1;
__REG32 :27;
} __OTG_clock_bits;
/* OTG I2C_TX/I2C_RX Register */
typedef union{
//I2C_RX
struct {
__REG32 RX_Data : 8;
__REG32 :24;
};
//I2C_TX
struct {
__REG32 TX_Data : 8;
__REG32 START : 1;
__REG32 STOP : 1;
__REG32 :22;
};
} __otg_i2c_rx_tx_bits;
/* OTG I2C_STS Register */
typedef struct{
__REG32 TDI : 1;
__REG32 AFI : 1;
__REG32 NAI : 1;
__REG32 DRMI : 1;
__REG32 DRSI : 1;
__REG32 Active : 1;
__REG32 SCL : 1;
__REG32 SDA : 1;
__REG32 RFF : 1;
__REG32 RFE : 1;
__REG32 TFF : 1;
__REG32 TFE : 1;
__REG32 :20;
} __otg_i2c_sts_bits;
/* OTG I2C_CTL Register */
typedef struct{
__REG32 TDIE : 1;
__REG32 AFIE : 1;
__REG32 NAIE : 1;
__REG32 DRMIE : 1;
__REG32 DRSIE : 1;
__REG32 RFFIE : 1;
__REG32 RFDAIE : 1;
__REG32 TFFIE : 1;
__REG32 SRST : 1;
__REG32 :23;
} __otg_i2c_ctl_bits;
/* CAN acceptance filter mode register */
typedef struct {
__REG32 AccOff :1;
__REG32 AccBP :1;
__REG32 eFCAN :1;
__REG32 :29;
} __afmr_bits;
/* CAN central transmit status register */
typedef struct {
__REG32 TS :4;
__REG32 :4;
__REG32 TBS :4;
__REG32 :4;
__REG32 TCS :4;
__REG32 :12;
} __cantxsr_bits;
/* CAN central receive status register */
typedef struct {
__REG32 RS :4;
__REG32 :4;
__REG32 RBS :4;
__REG32 :4;
__REG32 DOS :4;
__REG32 :12;
} __canrxsr_bits;
/* CAN miscellaneous status register */
typedef struct {
__REG32 ES :4;
__REG32 :4;
__REG32 BS :4;
__REG32 :20;
} __canmsr_bits;
/* CAN mode register */
typedef struct {
__REG32 RM :1;
__REG32 LOM :1;
__REG32 STM :1;
__REG32 TPM :1;
__REG32 SM :1;
__REG32 RPM :1;
__REG32 :1;
__REG32 TM :1;
__REG32 :24;
} __canmod_bits;
/* CAN command register */
typedef struct {
__REG32 TR :1;
__REG32 AT :1;
__REG32 RRB :1;
__REG32 CDO :1;
__REG32 SRR :1;
__REG32 STB1 :1;
__REG32 STB2 :1;
__REG32 STB3 :1;
__REG32 :24;
} __cancmr_bits;
/* CAN global status register */
typedef struct {
__REG32 RBS :1;
__REG32 DOS :1;
__REG32 TBS :1;
__REG32 TCS :1;
__REG32 RS :1;
__REG32 TS :1;
__REG32 ES :1;
__REG32 BS :1;
__REG32 :8;
__REG32 RXERR :8;
__REG32 TXERR :8;
} __cangsr_bits;
/* CAN interrupt capture register */
typedef struct {
__REG32 RI :1;
__REG32 TI1 :1;
__REG32 EI :1;
__REG32 DOI :1;
__REG32 WUI :1;
__REG32 EPI :1;
__REG32 ALI :1;
__REG32 BEI :1;
__REG32 IDI :1;
__REG32 TI2 :1;
__REG32 TI3 :1;
__REG32 :5;
__REG32 ERRBIT :5;
__REG32 ERRDIR :1;
__REG32 ERRC :2;
__REG32 ALCBIT :8;
} __canicr_bits;
/* CAN interrupt enable register */
typedef struct {
__REG32 RIE :1;
__REG32 TIE1 :1;
__REG32 EIE :1;
__REG32 DOIE :1;
__REG32 WUIE :1;
__REG32 EPIE :1;
__REG32 ALIE :1;
__REG32 BEIE :1;
__REG32 IDIE :1;
__REG32 TIE2 :1;
__REG32 TIE3 :1;
__REG32 :21;
} __canier_bits;
/* CAN bus timing register */
typedef struct {
__REG32 BRP :10;
__REG32 :4;
__REG32 SJW :2;
__REG32 TSEG1 :4;
__REG32 TSEG2 :3;
__REG32 SAM :1;
__REG32 :8;
} __canbtr_bits;
/* CAN error warning limit register */
typedef struct {
__REG32 EWL :8;
__REG32 :24;
} __canewl_bits;
/* CAN status register */
typedef struct {
__REG32 RBS :1;
__REG32 DOS :1;
__REG32 TBS1 :1;
__REG32 TCS1 :1;
__REG32 RS :1;
__REG32 TS1 :1;
__REG32 ES :1;
__REG32 BS :1;
__REG32 /*RBS*/ :1;
__REG32 /*DOS*/ :1;
__REG32 TBS2 :1;
__REG32 TCS2 :1;
__REG32 /*RS*/ :1;
__REG32 TS2 :1;
__REG32 /*ES*/ :1;
__REG32 /*BS*/ :1;
__REG32 /*RBS*/ :1;
__REG32 /*DOS*/ :1;
__REG32 TBS3 :1;
__REG32 TCS3 :1;
__REG32 /*RS*/ :1;
__REG32 TS3 :1;
__REG32 /*ES*/ :1;
__REG32 /*BS*/ :1;
__REG32 :8;
} __cansr_bits;
/* CAN rx frame status register */
typedef struct {
__REG32 IDIndex :10;
__REG32 BP :1;
__REG32 :5;
__REG32 DLC :4;
__REG32 :10;
__REG32 RTR :1;
__REG32 FF :1;
} __canrfs_bits;
/* CAN rx identifier register */
typedef union {
//CANxRID
struct {
__REG32 ID10_0 :11;
__REG32 :21;
};
//CANxRID
struct {
__REG32 ID29_18 :11;
__REG32 :21;
};
//CANxRID
struct {
__REG32 ID29_0 :29;
__REG32 :3;
};
} __canrid_bits;
/* CAN rx data register A */
typedef struct {
__REG32 Data1 :8;
__REG32 Data2 :8;
__REG32 Data3 :8;
__REG32 Data4 :8;
} __canrda_bits;
/* CAN rx data register B */
typedef struct {
__REG32 Data5 :8;
__REG32 Data6 :8;
__REG32 Data7 :8;
__REG32 Data8 :8;
} __canrdb_bits;
/* CAN tx frame information register */
typedef struct {
__REG32 PRIO :8;
__REG32 :8;
__REG32 DLC :4;
__REG32 :10;
__REG32 RTR :1;
__REG32 FF :1;
} __cantfi_bits;
/* CAN tx identifier register */
typedef union {
//CANxTIDy
struct {
__REG32 ID10_0 :11;
__REG32 :21;
};
//CANxTIDy
struct {
__REG32 ID29_18 :11;
__REG32 :21;
};
//CANxTIDy
struct {
__REG32 ID29_0 :29;
__REG32 :3;
};
} __cantid_bits;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -