📄 bsp.c
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/*
*********************************************************************************************************
* NXP LPC2378
* Keil MCB2300 Board Support Package
*
* (c) Copyright 2005, Micrium, Weston, FL
* All Rights Reserved
*
*
* File : BSP.C
* By : Eric Shufro
*********************************************************************************************************
*/
#define BSP_GLOBALS
#include <includes.h>
/*
*********************************************************************************************************
* CONFIGURATION
*********************************************************************************************************
*/
#define BSP_DEBUG 0
/*
*********************************************************************************************************
* CONFIGURATION CHECKING
*********************************************************************************************************
*/
#if BSP_DEBUG > 0
#warning "BSP_DEBUG should be set to 0 for proper operation of uC/OS-View"
#else
#warning "BSP_DEBUG should be set to 1 while debugging application code on the LPC2378"
#endif
/*
*********************************************************************************************************
* CONSTANTS
*********************************************************************************************************
*/
#define LCD_BIT_DATA0 (CPU_INT32U)(1 << 24)
#define LCD_BIT_DATA1 (CPU_INT32U)(1 << 25)
#define LCD_BIT_DATA2 (CPU_INT32U)(1 << 26)
#define LCD_BIT_DATA3 (CPU_INT32U)(1 << 27)
#define LCD_BIT_RS (CPU_INT32U)(1 << 28)
#define LCD_BIT_RW (CPU_INT32U)(1 << 29)
#define LCD_BIT_E (CPU_INT32U)(1 << 30)
/*
*********************************************************************************************************
* VARIABLES
*********************************************************************************************************
*/
static CPU_INT32U Tmr_ReloadCnts;
/*
*********************************************************************************************************
* PROTOTYPES
*********************************************************************************************************
*/
static void BSP_PLL_Init(void);
static void BSP_MAM_Init(void);
static void BSP_IO_Init(void);
#ifdef DISP_MODULE_PRESENT
static void DispE_High(void);
static void DispE_Low(void);
static void DispRW_High(void);
static void DispRW_Low (void);
#endif
static void Tmr_TickInit(void);
/*
*********************************************************************************************************
* BSP INITIALIZATION
*
* Description : This function should be called by your application code before you make use of any of the
* functions found in this module.
*
* Arguments : none
*********************************************************************************************************
*/
void BSP_Init (void)
{
BSP_PLL_Init(); /* Initialize the PLL */
BSP_MAM_Init(); /* Initialize the Memory Acceleration Module */
BSP_IO_Init(); /* Initialize the board's I/Os */
VIC_Init(); /* Initialize the Vectored Interrupt Controller */
LED_Init(); /* Initialize the I/Os for the LED controls */
Tmr_TickInit(); /* Initialize the uC/OS-II tick interrupt */
}
/*
*********************************************************************************************************
* Set the CPU Clock Frequency
*
* Description: This function sets up and activates the PLL
*
* Notes : 1) The PLL output frequency is calculated by the following formula:
* Fcco = 2 * Fin * m / n, where Fin is the PLL input clock. In
* this particular case, Fin is set to the Main Oscillator
* whose frequency is #define'd in bsp.h. M is the PLL
* clock multiplier. M must be written to the PLLCFG register
* as the desired multiplier - 1. N is the PLL clock divider
* and must be written to PLLCFG as the desired divider - 1.
*
* 2) Fcco must be between 250 and 550 MHz. The ARM Core clock
* must never exceed 72 MHz. Use cClkDiv to divide Fcco accordingly.
*
* 3) When using the USB device, you must choose Fcco as a multiple
* of 96 MHz, and then use usbClkDiv to divide Fcco to exactly
* 48 MHz.
*
* 4) In this example, Fin = 12MHz, M = 12, N = 1, cClkDiv = 6 and usbClkDiv = 6.
* Therefore, Fcco = 2 * Fin * M / N = (2 * 12 * 12 / 1) = 288MHz.
* The processor clock = (Fcco / cClkDiv) = (288MHz / 6) = 48MHz.
* Finally, the USB clock = (Fcco / usbClkDib) = (288MHz / 6) = 48MHz.
*
* 5) Early revisions of the part have a PLL errata preventing Fcco from
* being greater than 288MHz.
*
* 6) For later revisions, M = 20, cCLKDiv = 8, and usbClkDiv = 10 yield
* 60MHz for the processor clock and 48MHz for the USB clock.
*********************************************************************************************************
*/
void BSP_PLL_Init (void)
{
#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */
OS_CPU_SR cpu_sr = 0;
#endif
CPU_INT32U m;
CPU_INT32U n;
CPU_INT32U cClkDiv;
CPU_INT32U usbClkDiv;
m = 11; /* PLL Multiplier = 20, MSEL bits = 12 - 1 = 11 */
n = 0; /* PLL Divider = 1, NSEL bits = 1 - 1 = 0 */
cClkDiv = 5; /* Configure the ARM Core clock div to 6. CCLKSEL = 6 - 1 */
usbClkDiv = 5; /* Configure the USB clock divider to 6, USBSEL = 6 - 1 */
if ((PLLSTAT & (1 << 25)) > 0) { /* If the PLL is already running */
CPU_CRITICAL_ENTER();
PLLCON &= ~(1 << 1); /* Disconnect the PLL */
PLLFEED = 0xAA; /* PLL register update sequence, 0xAA, 0x55 */
PLLFEED = 0x55;
CPU_CRITICAL_EXIT();
}
CPU_CRITICAL_ENTER();
PLLCON &= ~(1 << 0); /* Disable the PLL */
PLLFEED = 0xAA; /* PLL register update sequence, 0xAA, 0x55 */
PLLFEED = 0x55;
CPU_CRITICAL_EXIT();
SCS &= ~(1 << 4); /* OSCRANGE = 0, Main OSC is between 1 and 20 Mhz */
SCS |= (1 << 5); /* OSCEN = 1, Enable the main oscillator */
while ((SCS & (1 << 6)) == 0) { /* Wait until OSCSTAT is set (Main OSC ready to be used) */
;
}
CLKSRCSEL = (1 << 0); /* Select main OSC, 12MHz, as the PLL clock source */
CPU_CRITICAL_ENTER();
PLLCFG = (m << 0) | (n << 16); /* Configure the PLL multiplier and divider */
PLLFEED = 0xAA; /* PLL register update sequence, 0xAA, 0x55 */
PLLFEED = 0x55;
CPU_CRITICAL_EXIT();
CPU_CRITICAL_ENTER();
PLLCON |= (1 << 0); /* Enable the PLL */
PLLFEED = 0xAA; /* PLL register update sequence, 0xAA, 0x55 */
PLLFEED = 0x55;
CPU_CRITICAL_EXIT();
CCLKCFG = cClkDiv; /* Configure the ARM Core Processor clock divider */
USBCLKCFG = usbClkDiv; /* Configure the USB clock divider */
while ((PLLSTAT & (1 << 26)) == 0) { /* Wait for PLOCK to become set */
;
}
CPU_CRITICAL_ENTER();
PLLCON |= (1 << 1); /* Connect the PLL. The PLL is now the active clock source */
PLLFEED = 0xAA; /* PLL register update sequence, 0xAA, 0x55 */
PLLFEED = 0x55;
CPU_CRITICAL_EXIT();
while ((PLLSTAT & (1 << 25)) == 0) { /* Wait PLLC, the PLL connect status bit to become set */
;
}
}
/*
*********************************************************************************************************
* BSP_MAM_Init()
*
* Description : This function initializes the Memory Acceleration Module
*
* Arguements : None
* Returns : None
* Notes : None
*********************************************************************************************************
*/
void BSP_MAM_Init (void)
{
CPU_INT32U cClkFrq;
cClkFrq = BSP_CPU_ClkFreq(); /* Get the current core clock frequency */
MAMCR = 0; /* Disable MAM functionality */
if (cClkFrq < 20000000) { /* Compare current clock frequency with MAM modes */
MAMTIM = 1; /* Set MAM fetch cycles to 1 processor clock in duration */
}
if (cClkFrq < 40000000) {
MAMTIM = 2; /* Set MAM fetch cycles to 2 processor clock in duration */
}
if (cClkFrq >= 40000000) {
MAMTIM = 3; /* Set MAM fetch cycles to 3 processor clock in duration */
}
MAMCR = 2; /* Enable full MAM functionality */
}
/*
*********************************************************************************************************
* Get the CPU Clock Frequency
*
* Description : This function reads CPU registers to determine the CPU clock frequency
*
* Arguements : None
* Returns : The CPU Core clock in Hz
* Notes : None
*********************************************************************************************************
*/
CPU_INT32U BSP_CPU_ClkFreq (void)
{
CPU_INT32U msel;
CPU_INT32U nsel;
CPU_INT32U Fin;
CPU_INT32U pllClkFrq; /* When the PLL is enabled, this is Fcco */
CPU_INT32U cClkDiv;
CPU_INT32U cClkFrq;
switch (CLKSRCSEL & 0x03) { /* Determine the current clock source */
case 0:
Fin = IRC_OSC_FRQ;
break;
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