hib.h

H3 M-system NAND flash driver in Linux OS, M-DOC driver

/******************************************************************************
 *                                                                            *
 * Project: DOC Driver for Linux 2.4 Block device driver for mDOC H3  family  *
 * of devices under Linux kernel 2.4.                                         *
 *                                                                            *
 *   Version: 1.0                                                             *
 *   Email questions to: [e-mail]                               *
 *   Copyright (C) SanDisk IL Ltd. 1995 - 2007                                *
 *   SanDisk IL Ltd., 7 Atir Yeda Street, Kfar Saba 44425, Israel             *
 *                                                                            *
 ******************************************************************************
 *                                                                            *
 * This program is free software; you can redistribute it and/or modify it    *
 * under the terms of the GNU General Public License as published by the Free *
 * Software Foundation; either version 2 of the License, or any later version.*
 * This program is distributed in the hope that it will be useful, but WITHOUT*
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or      *
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for  *
 * more details, which is set forth in the readme.txt file.                   *
 * You should have received a copy of the GNU General Public License along    *
 * with this program; if not, write to the Free Software Foundation, Inc., 51 *
 * Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA                    *
 *                                                                            *
 * This License does not grant you any right to use the trademarks, service   *
 * marks or logos of SanDisk IL Ltd. or SanDisk Corporation.                  *
 * Subject to the foregoing, SanDisk IL Ltd., for itself and on behalf of its *
 * licensors, hereby reserves all intellectual property rights in the program,*
 * except for the rights expressly granted in this License.                   *
 *                                                                            *
 ******************************************************************************/
/*
 * $Log:   V:/PVCSDB/DiskOnChip/archives/general storage/TrueFFS (7.x)/src/H3/Include/hib.h-arc  $
 * 
 *    Rev 1.22   Sep 11 2006 13:45:26   yaniv.iarovici
 * Legal header added
 * 
 *    Rev 1.21   Aug 09 2006 17:26:56   Polina.Marimont
 * initial for DOC Driver 1.0
 * 
 */

#ifndef HIB_H
#define HIB_H

/*  HIB registers   */
/*  =============   */

extern FLWord gMemWindowType;
extern FLDword gDochMemWinSize;

extern FLWord gHibCoreAddress;
extern FLWord gHibContRegAreaOffset;
extern FLWord gHibDataPortAreaOffset;
extern FLWord gHibConfigRegAreaOffset;

/*Memory window type and size*/
/*---------------------------*/
/*Type*/
#define MEM_WIN_8KB		0
#define MEM_WIN_128KB	1

/*Size*/
#define DOCH_MEM_WIN_SIZE				(gDochMemWinSize)
#ifdef DOCH_32K_SLIDING_WINDOW
	#define DOCH_MEM_WIN_SIZE_8KB           0x8000  /*32KB*/
	#define DOCH_MEM_WIN_SIZE_128KB         0x8000	/*32KB*/
#else /*DOCH_32K_SLIDING_WINDOW*/
	#define DOCH_MEM_WIN_SIZE_8KB           0x2000  /*8KB*/
	#define DOCH_MEM_WIN_SIZE_128KB         0x20000	/*128KB*/
#endif /*DOCH_32K_SLIDING_WINDOW*/

/*Register Areas*/
/*--------------*/

/*Core Address*/
#define HIB_CORE_ADDRESS					(gHibCoreAddress)

#define HIB_CORE_ADDRESS_8KB				0x0000
#ifdef DOCH_32K_SLIDING_WINDOW
	#define HIB_CORE_ADDRESS_128KB			0x0000
#else /*DOCH_32K_SLIDING_WINDOW*/
	#define HIB_CORE_ADDRESS_128KB			0x8000
#endif /*DOCH_32K_SLIDING_WINDOW*/

/*Area Offset*/
#ifndef DOCH_CONT_REG_AREA_OFFSET
	#define DOCH_CONT_REG_AREA_OFFSET			(gHibContRegAreaOffset)
#endif /*DOCH_CONT_REG_AREA_OFFSET*/

#ifndef DOCH_DATA_PORT_AREA_OFFSET
	#define DOCH_DATA_PORT_AREA_OFFSET			(gHibDataPortAreaOffset)
#endif /*DOCH_DATA_PORT_AREA_OFFSET*/

#ifndef DOCH_CONFIG_REG_AREA_OFFSET
	#define DOCH_CONFIG_REG_AREA_OFFSET			(gHibConfigRegAreaOffset)
#endif /*DOCH_CONFIG_REG_AREA_OFFSET*/

/*8KB Offsets*/
#define DOCH_CONT_REG_AREA_8KB_OFFSET		0x0800
#define DOCH_DATA_PORT_AREA_8KB_OFFSET		0x1000
#define DOCH_CONFIG_REG_AREA_8KB_OFFSET		0x1400

/*128KB Offsets*/
#define DOCH_CONT_REG_AREA_128KB_OFFSET				0
#define DOCH_DATA_PORT_AREA_128KB_OFFSET			0x0800
#define DOCH_CONFIG_REG_AREA_128KB_OFFSET			0x1400
#define DOCH_PRIMARY_SECONDARY_AREA_128KB_OFFSET	0x1800

/*Area Address*/
#define DOCH_CONT_REG_AREA				(HIB_CORE_ADDRESS + DOCH_CONT_REG_AREA_OFFSET)
#define DOCH_DATA_PORT_AREA				(HIB_CORE_ADDRESS + DOCH_DATA_PORT_AREA_OFFSET)
#define DOCH_CONFIG_REG_AREA			(HIB_CORE_ADDRESS + DOCH_CONFIG_REG_AREA_OFFSET)
#define DOCH_PRIMARY_SECONDARY_AREA		(HIB_CORE_ADDRESS + DOCH_PRIMARY_SECONDARY_AREA_128KB_OFFSET)


/* Control registers - offset is from DOCH_CONT_REG_AREA*/
/*------------------------------------------------------*/
#define DOCH_VERSION_REG                (DOCH_CONT_REG_AREA + 0xC1A)
#define DOCH_LAST_ACCESS_ADDR_REG       (DOCH_CONT_REG_AREA + 0xC1E)
#define DOCH_PAGED_RAM_CMD_REG          (0x30)
#define DOCH_PAGED_RAM_SELECT_REG       (0x70)
#define DOCH_PAGED_RAM_COTP_STAT_DL_REG (0x78)
#define DOCH_PAGED_RAM_COTP_SELECT_REG  (0x7C)
#define DOCH_PAGED_RAM_UNIQUE_ID_DL     (0x80)

/* Host Configuration registers - offset is from DOCH_CONFIG_REG_AREA*/
/*-------------------------------------------------------------------*/
#define HIB_CHIPID1_REG                 (DOCH_CONFIG_REG_AREA)
#define HIB_BURST_WRITE_MODE_CTRL_REG   (DOCH_CONFIG_REG_AREA + 0x02)
#define HIB_BURST_WRITE_MODE_EXIT_REG   (DOCH_CONFIG_REG_AREA + 0x04)
#define HIB_DOWNLOAD_CONTROL_REG        (DOCH_CONFIG_REG_AREA + 0x06)
#define HIB_IPL_CONTROL_REG             (DOCH_CONFIG_REG_AREA + 0x08)
#define HIB_WARM_BOOT_REG               (DOCH_CONFIG_REG_AREA + 0x0A)
#define HIB_POWER_DOWN_REG              (DOCH_CONFIG_REG_AREA + 0x0C)
#define HIB_DMA_CTRL_REG                (DOCH_CONFIG_REG_AREA + 0x0E)
#define HIB_SW_LOCK_REG                 (DOCH_CONFIG_REG_AREA + 0x10)
#define HIB_ENDIAN_CTRL_REG             (DOCH_CONFIG_REG_AREA + 0x12)
#define HIB_OPERATION_MODE_REG          (DOCH_CONFIG_REG_AREA + 0x14)
#define HIB_POWER_MODE_REG              (DOCH_CONFIG_REG_AREA + 0x16)
#define HIB_DMA_NEGATION_REG            (DOCH_CONFIG_REG_AREA + 0x18)
#define HIB_CHIPID2_REG                 (DOCH_CONFIG_REG_AREA + 0x22)
#define HIB_BURST_READ_MODE_CTRL_REG    (DOCH_CONFIG_REG_AREA + 0x24)




/*Specific per-register values*/
/*============================*/
/*Burst Read/Write Mode Control Register*/
#define HIB_BURST_HOLD_1_CLK        0x0000
#define HIB_BURST_HOLD_2_CLK        0x2000

#define HIB_BURST_LEN_4_CYC         0x0000
#define HIB_BURST_LEN_8_CYC         0x0800
#define HIB_BURST_LEN_16_CYC        0x1000
#define HIB_BURST_LEN_32_CYC        0x1800

#define HIB_BURST_DISABLE           0x0000
#define HIB_BURST_ENABLE            0x0001

/*Download Control Register*/
#define HIB_DOWNLOAD_COMPLETED      0x0000
#define HIB_DOWNLOAD_IN_PROCESS     0x0001

/*IPL Control Register*/
#define HIB_IPL_WRITE_DISABLE       0x0000
#define HIB_IPL_WRITE_ENABLE        0x0001

#define HIB_IPL_NOT_READY_FOR_WRITE 0x0000
#define HIB_IPL_READY_FOR_WRITE     0x0002

/*Warm Boot Register*/
#define HIB_WARM_RST_POLARITY_LOW   0x0000
#define HIB_WARM_RST_POLARITY_HIGH  0x0001

#define HIB_WARM_RST_BURST_ON       0x0000
#define HIB_WARM_RST_BURST_NO_CHNG  0x0002

/*Power Down Register*/
#define HIB_DPD_PIN_POLARITY_LOW    0x0000
#define HIB_DPD_PIN_POLARITY_LOW    0x0000

#define HIB_DPD_PIN_DISABLE         0x0000
#define HIB_DPD_PIN_ENABLE          0x0002

/*DMA Control Register*/
#define HIB_DMA_REQ_DISABLE         0x0000
#define HIB_DMA_REQ_ENABLE          0x0001

#define HIB_DMA_REQ_POL_HIGH        0x0000
#define HIB_DMA_REQ_POL_LOW         0x0002

#define HIB_DMA_REQ_LEVEL           0x0000
#define HIB_DMA_REQ_EDGE            0x0004

/*S/W Lock Register*/
#define HIB_SW_LOCK_ON              0x0001

/*Endian Control Register*/
#define HIB_END_SWAP_OFF            0x0000
#define HIB_END_SWAP_ON             0x0101

/*Operation Mode Register*/
#define HIB_NON_PIPE_ACCESS         0x00
#define HIB_PIPE_ACCESS             0x01

#define HIB_NO_ADDR_SHIFT           0x00
#define HIB_ADDR_SHIFT              0x02

/*Power Mode Register*/
#define HIB_POWER_DOWN              0x0001

/*Paged RAM Command Register*/
#define HIB_PAGED_RAM_ENABLE_SELECT 0x71

/*Paged RAM Select Register*/
#define HIB_PAGED_RAM_SEQ           0x0080


/*Folloing array is used to conserve every write to a configuration register.
The purpose is to enable reseting the device registers in case of power loss*/
typedef struct {
    FLWord wBurstWriteModeCtrl;
    FLWord wIPLCtrl;
    FLWord wPowerDown;
    FLWord wDMACtrl;
    FLWord wSWLock;
    FLWord wEndianCtrl;
    FLWord wEndianNegation;
    FLWord wOperationMode;
    FLWord wBurstReadModeCtrl;
} DOCH_ConfigRegsValue;

typedef struct {
    FLWord wBurstWriteModeCtrlSet;
    FLWord wIPLCtrlSet;
    FLWord wPowerDownSet;
    FLWord wDMACtrlSet;
    FLWord wSWLockSet;
    FLWord wEndianCtrlSet;
    FLWord wEndianNegationSet;
    FLWord wOperationModeSet;
    FLWord wBurstReadModeCtrlSet;
} DOCH_ConfigRegsSet;

/* Changing device memory window size (8/128 KB)*/
#define DOCH_PAGED_RAM_TIMEOUT		300000L
#define DOCH_READ_PAGED_RAM_DELAY	20

typedef enum {
	DOCH_MEM_WIN_SIZE_8K			= 0,
	DOCH_MEM_WIN_SIZE_128K			= 1,	/*Regular, with no pull-downs on high address bits*/
	DOCH_MEM_WIN_SIZE_128K_SPECIAL	= 2		/*Special, with pull-downs on high address bits*/
} DOCH_MemWinSize;

#endif /*HIB_H*/