📄 de2_nios_host_mouse_vga.v
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output OTG_WR_N; // ISP1362 Read
output OTG_RST_N; // ISP1362 Reset
output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
input OTG_INT0; // ISP1362 Interrupt 0
input OTG_INT1; // ISP1362 Interrupt 1
input OTG_DREQ0; // ISP1362 DMA Request 0
input OTG_DREQ1; // ISP1362 DMA Request 1
output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////////////////
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
//////////////////// SD Card Interface ////////////////////////
inout SD_DAT; // SD Card Data
inout SD_DAT3; // SD Card Data 3
inout SD_CMD; // SD Card Command Signal
output SD_CLK; // SD Card Clock
//////////////////////// I2C ////////////////////////////////
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
//////////////////////// PS2 ////////////////////////////////
inout PS2_DAT; // PS2 Data
inout PS2_CLK; // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
input TDI; // CPLD -> FPGA (data in)
input TCK; // CPLD -> FPGA (clk)
input TCS; // CPLD -> FPGA (CS)
output TDO; // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
//////////////// Ethernet Interface ////////////////////////////
inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
output ENET_CS_N; // DM9000A Chip Select
output ENET_WR_N; // DM9000A Write
output ENET_RD_N; // DM9000A Read
output ENET_RST_N; // DM9000A Reset
input ENET_INT; // DM9000A Interrupt
output ENET_CLK; // DM9000A Clock 25 MHz
//////////////////// Audio CODEC ////////////////////////////
inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////// TV Devoder ////////////////////////////
input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
input TD_HS; // TV Decoder H_SYNC
input TD_VS; // TV Decoder V_SYNC
output TD_RESET; // TV Decoder Reset
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
wire CPU_CLK;
wire CPU_RESET;
wire CLK_18_4;
wire CLK_25;
// Flash
assign FL_RST_N = 1'b1;
// 16*2 LCD Module
assign LCD_ON = 1'b1; // LCD ON
assign LCD_BLON = 1'b1; // LCD Back Light
// All inout port turn to tri-state
assign SD_DAT = 1'bz;
assign AUD_ADCLRCK = AUD_DACLRCK;
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
// Disable USB speed select
assign OTG_FSPEED = 1'bz;
assign OTG_LSPEED = 1'bz;
// Turn On TV Decoder
assign TD_RESET = 1'b1;
// Set SD Card to SD Mode
assign SD_DAT3 = 1'b1;
// VGA
assign VGA_CLK = CLK_25;
assign VGA_R[1:0] = VGA_BLANK?2'b11:2'b00;
assign VGA_G[1:0] = VGA_BLANK?2'b11:2'b00;
assign VGA_B[1:0] = VGA_BLANK?2'b11:2'b00;
Reset_Delay delay1 (.iRST(KEY[0]),.iCLK(CLOCK_50),.oRESET(CPU_RESET));
SDRAM_PLL PLL1 (.inclk0(CLOCK_50),.c0(DRAM_CLK),.c1(CPU_CLK),.c2(CLK_25));
Audio_PLL PLL2 (.areset(!CPU_RESET),.inclk0(CLOCK_27),.c0(CLK_18_4));
system_0 u0 (
// global signals:
.clk(CPU_CLK),
.reset_n(CPU_RESET),
// the_Audio_0
.iCLK_18_4_to_the_Audio_0(CLK_18_4),
.oAUD_BCK_from_the_Audio_0(AUD_BCLK),
.oAUD_DATA_from_the_Audio_0(AUD_DACDAT),
.oAUD_LRCK_from_the_Audio_0(AUD_DACLRCK),
.oAUD_XCK_from_the_Audio_0(AUD_XCK),
// the_VGA_0
.R_from_the_vga_controller_0 (VGA_R[9:2]),
.G_from_the_vga_controller_0 (VGA_G[9:2]),
.B_from_the_vga_controller_0 (VGA_B[9:2]),
.blank_n_from_the_vga_controller_0 (VGA_BLANK),
.hsync_from_the_vga_controller_0 (VGA_HS),
.sync_n_from_the_vga_controller_0 (VGA_SYNC),
.vga_clk_to_the_vga_controller_0 (VGA_CLK),
.vsync_from_the_vga_controller_0 (VGA_VS),
// PS2
.PS2_CLK_to_and_from_the_ps2_0 (PS2_CLK),
.PS2_DAT_to_and_from_the_ps2_0 (PS2_DAT),
// the_SD_CLK
.out_port_from_the_SD_CLK(SD_CLK),
// the_SD_CMD
.bidir_port_to_and_from_the_SD_CMD(SD_CMD),
// the_SD_DAT
.bidir_port_to_and_from_the_SD_DAT(SD_DAT),
// the_SEG7_Display
.oSEG0_from_the_SEG7_Display(HEX0),
.oSEG1_from_the_SEG7_Display(HEX1),
.oSEG2_from_the_SEG7_Display(HEX2),
.oSEG3_from_the_SEG7_Display(HEX3),
.oSEG4_from_the_SEG7_Display(HEX4),
.oSEG5_from_the_SEG7_Display(HEX5),
.oSEG6_from_the_SEG7_Display(HEX6),
.oSEG7_from_the_SEG7_Display(HEX7),
// the_DM9000A
.ENET_CLK_from_the_DM9000A(ENET_CLK),
.ENET_CMD_from_the_DM9000A(ENET_CMD),
.ENET_CS_N_from_the_DM9000A(ENET_CS_N),
.ENET_DATA_to_and_from_the_DM9000A(ENET_DATA),
.ENET_INT_to_the_DM9000A(ENET_INT),
.ENET_RD_N_from_the_DM9000A(ENET_RD_N),
.ENET_RST_N_from_the_DM9000A(ENET_RST_N),
.ENET_WR_N_from_the_DM9000A(ENET_WR_N),
.iOSC_50_to_the_DM9000A(CLOCK_50),
// the_ISP1362
.OTG_ADDR_from_the_ISP1362(OTG_ADDR),
.OTG_CS_N_from_the_ISP1362(OTG_CS_N),
.OTG_DATA_to_and_from_the_ISP1362(OTG_DATA),
.OTG_INT0_to_the_ISP1362(OTG_INT0),
.OTG_INT1_to_the_ISP1362(OTG_INT1),
.OTG_RD_N_from_the_ISP1362(OTG_RD_N),
.OTG_RST_N_from_the_ISP1362(OTG_RST_N),
.OTG_WR_N_from_the_ISP1362(OTG_WR_N),
// the_button_pio
.in_port_to_the_button_pio(KEY),
// the_lcd_16207_0
.LCD_E_from_the_lcd_16207_0(LCD_EN),
.LCD_RS_from_the_lcd_16207_0(LCD_RS),
.LCD_RW_from_the_lcd_16207_0(LCD_RW),
.LCD_data_to_and_from_the_lcd_16207_0(LCD_DATA),
// the_led_green
.out_port_from_the_led_green(LEDG),
// the_led_red
.out_port_from_the_led_red(LEDR),
// the_sdram_0
.zs_addr_from_the_sdram_0(DRAM_ADDR),
.zs_ba_from_the_sdram_0({DRAM_BA_1,DRAM_BA_0}),
.zs_cas_n_from_the_sdram_0(DRAM_CAS_N),
.zs_cke_from_the_sdram_0(DRAM_CKE),
.zs_cs_n_from_the_sdram_0(DRAM_CS_N),
.zs_dq_to_and_from_the_sdram_0(DRAM_DQ),
.zs_dqm_from_the_sdram_0({DRAM_UDQM,DRAM_LDQM}),
.zs_ras_n_from_the_sdram_0(DRAM_RAS_N),
.zs_we_n_from_the_sdram_0(DRAM_WE_N),
// the_sram_0
.SRAM_ADDR_from_the_sram_0(SRAM_ADDR),
.SRAM_CE_N_from_the_sram_0(SRAM_CE_N),
.SRAM_DQ_to_and_from_the_sram_0(SRAM_DQ),
.SRAM_LB_N_from_the_sram_0(SRAM_LB_N),
.SRAM_OE_N_from_the_sram_0(SRAM_OE_N),
.SRAM_UB_N_from_the_sram_0(SRAM_UB_N),
.SRAM_WE_N_from_the_sram_0(SRAM_WE_N),
// the_switch_pio
.in_port_to_the_switch_pio(SW),
// the_tri_state_bridge_0_avalon_slave
.select_n_to_the_cfi_flash_0(FL_CE_N),
.tri_state_bridge_0_address(FL_ADDR),
.tri_state_bridge_0_data(FL_DQ),
.tri_state_bridge_0_readn(FL_OE_N),
.write_n_to_the_cfi_flash_0(FL_WE_N),
// the_uart_0
.rxd_to_the_uart_0(UART_RXD),
.txd_from_the_uart_0(UART_TXD)
);
I2C_AV_Config u1 ( // Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[0]),
// I2C Side
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT) );
endmodule⌨️ 快捷键说明
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