📄 rtl8019as.c
字号:
/*********************************************************************
*
* Realtek RTL8019AS MAC Module for Microchip TCP/IP Stack
*
*********************************************************************
* FileName: RTL8019AS.c
* Dependencies: string.h
* stacktsk.h
* helpers.h
* mac.h
* Processor: PIC18
* Complier: MCC18 v3.03 or higher
* Company: Microchip Technology, Inc.
*
* Software License Agreement
*
* This software is owned by Microchip Technology Inc. ("Microchip")
* and is supplied to you for use exclusively as described in the
* associated software agreement. This software is protected by
* software and other intellectual property laws. Any use in
* violation of the software license may subject the user to criminal
* sanctions as well as civil liability. Copyright 2006 Microchip
* Technology Inc. All rights reserved.
*
* This software is provided "AS IS." MICROCHIP DISCLAIMS ALL
* WARRANTIES, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, NOT LIMITED
* TO MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
* INFRINGEMENT. Microchip shall in no event be liable for special,
* incidental, or consequential damages.
*
*
* Author Date Comment
*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Nilesh Rajbharti 4/27/00 Original (Rev 1.0)
* Nilesh Rajbharti 2/9/02 Cleanup
* Nilesh Rajbharti 5/22/02 Rev 2.0 (See version.log for detail)
* Nilesh Rajbharti 3/21/03 Fixed MACIsTxReady() bug where upon
* certain bus collision, this would always
* return FLASE causing Stack to not handle
* any incoming packets at all.
* Howard Schlunder 8/09/06 Slight modifications to work with 3.75
********************************************************************/
#define THIS_IS_MAC_LAYER
#include <string.h>
#include "..\Include\StackTsk.h"
#include "..\Include\Helpers.h"
#include "..\Include\MAC.h"
#include "..\Include\Delay.h"
#if defined(STACK_USE_SLIP)
#error Unexpected module is detected.
#error This file must not be linked when SLIP module is in use.
#endif
/*
* Hardware interface to NIC.
*/
#define NIC_DATAPORT (0x10)
#define NIC_RESET (0x1f)
/* Ethernet definitions.. */
#define MINFRAME 60
#define MINFRAMEC 64
#define CRCLEN 4
#define MAXFRAME 1514
#define MAXFRAMEC 1518
/* 8390 Network Interface Controller (NIC) page0 register offsets */
#define CMDR 0x00 /* command register for read & write */
#define PSTART 0x01 /* page start register for write */
#define PSTOP 0x02 /* page stop register for write */
#define BNRY 0x03 /* boundary reg for rd and wr */
#define TPSR 0x04 /* tx start page start reg for wr */
#define TXSTAT TPSR
#define TBCR0 0x05 /* tx byte count 0 reg for wr */
#define TBCR1 0x06 /* tx byte count 1 reg for wr */
#define ISR 0x07 /* interrupt status reg for rd and wr */
#define RSAR0 0x08 /* low byte of remote start addr */
#define RSAR1 0x09 /* hi byte of remote start addr */
#define RBCR0 0x0A /* remote byte count reg 0 for wr */
#define RBCR1 0x0B /* remote byte count reg 1 for wr */
#define RCR 0x0C /* rx configuration reg for wr */
#define TCR 0x0D /* tx configuration reg for wr */
#define DCR 0x0E /* data configuration reg for wr */
#define IMR 0x0F /* interrupt mask reg for wr */
/* NIC page 1 register offsets */
#define PAR0 0x01 /* physical addr reg 0 for rd and wr */
#define CURRP 0x07 /* current page reg for rd and wr */
#define MAR0 0x08 /* multicast addr reg 0 for rd and WR */
/* NIC page 3 register offsets */
#define RTL9346CR 0x01 /* RTL 9346 command reg */
#define RTL3 0x06 /* RTL config reg 3 */
#define NIC_PAGE_SIZE (256)
/* NIC RAM definitions */
#define RAMPAGES 0x20 /* Total number of 256-byte RAM pages */
#define TXSTART 0x40 /* Tx buffer start page - NE2000 mode */
#define TXPAGES (MAC_TX_BUFFER_COUNT * (MAC_TX_BUFFER_SIZE/NIC_PAGE_SIZE))
#define RXSTART (TXSTART+TXPAGES) /* Rx buffer start page */
#define RXSTOP (TXSTART+RAMPAGES-1) /* Last Rx buffer page */
#define DCRVAL 0x48 /* Value for data config reg */
/* 8-bit DMA, big-endian, 1 DMA, Normal */
#define RXPAGES (RXSTOP - RXSTART)
#define SET_NIC_READ() (NIC_DATA_TRIS = 0xff)
#define SET_NIC_WRITE() (NIC_DATA_TRIS = 0x00)
#define WRITE_NIC_ADDR(a) {NIC_ADDR_IO = a; NIC_ADDR_TRIS = 0xe0;}
typedef struct _IEEE_HEADER
{
MAC_ADDR DestMACAddr;
MAC_ADDR SourceMACAddr;
WORD_VAL Len;
BYTE LSAPControl[3];
BYTE OUI[3];
WORD_VAL Protocol;
} IEEE_HEADER;
#define ETHER_IP (0x00)
#define ETHER_ARP (0x06)
typedef struct _DATA_BUFFER
{
BYTE Index;
BOOL bFree;
} DATA_BUFFER;
static DATA_BUFFER TxBuffers[(TXPAGES*NIC_PAGE_SIZE)/MAC_TX_BUFFER_SIZE];
#define MAX_DATA_BUFFERS (sizeof(TxBuffers)/sizeof(TxBuffers[0]))
typedef struct _ETHER_HEADER
{
MAC_ADDR DestMACAddr;
MAC_ADDR SourceMACAddr;
WORD_VAL Type;
} ETHER_HEADER;
typedef struct _NE_RCR
{
unsigned char PRX:1;
unsigned char CRC:1;
unsigned char FAE:1;
unsigned char FO:1;
unsigned char MPA:1;
unsigned char PHY:1;
unsigned char DIS:1;
unsigned char DFR:1;
} NE_RCR;
typedef struct _NE_PREAMBLE
{
NE_RCR Status;
BYTE NextPacketPointer;
WORD ReceivedBytes;
MAC_ADDR DestMACAddr;
MAC_ADDR SourceMACAddr;
WORD_VAL Type;
} NE_PREAMBLE;
BYTE NICReadPtr; // Next page that will be used by NIC to load new packet.
BYTE NICCurrentRdPtr; // Page that is being read...
BYTE NICCurrentTxBuffer;
static void NICReset(void);
static void NICPut(BYTE reg, BYTE val);
static BYTE NICGet(BYTE reg);
static void NICSetAddr(WORD addr);
void MACInit(void)
{
BYTE i;
// On Init, all transmit buffers are free.
for ( i = 0; i < MAX_DATA_BUFFERS; i++ )
{
TxBuffers[i].Index = TXSTART + (i * (MAC_TX_BUFFER_SIZE/NIC_PAGE_SIZE));
TxBuffers[i].bFree = TRUE;
}
NICCurrentTxBuffer = 0;
NICReset();
DelayMs(2);
NICPut(NIC_RESET, NICGet(NIC_RESET));
// mimimum Delay of 1.6 ms
DelayMs(2);
// Continue only if reset state is entered.
if ( (NICGet(ISR) & 0x80) != 0 )
{
// Select Page 0
NICPut(CMDR, 0x21);
DelayMs(2);
// Initialize Data Configuration Register
NICPut(DCR, DCRVAL);
// Clear Remote Byte Count Registers
NICPut(RBCR0, 0);
NICPut(RBCR1, 0);
// Initialize Receive Configuration Register
NICPut(RCR, 0x04);
// Place NIC in LOOPBACK mode 1
NICPut(TCR, 0x02);
// Initialize Transmit buffer queue
NICPut(TPSR, TxBuffers[NICCurrentTxBuffer].Index);
// Initialize Receive Buffer Ring
NICPut(PSTART, RXSTART);
NICPut(PSTOP, RXSTOP);
NICPut(BNRY, (BYTE)(RXSTOP-1));
// Initialize Interrupt Mask Register
// Clear all status bits
NICPut(ISR, 0xff);
// No interrupt enabled.
NICPut(IMR, 0x00);
// Select Page 1
NICPut(CMDR, 0x61);
// Initialize Physical Address Registers
NICPut(PAR0+0, AppConfig.MyMACAddr.v[0]);
NICPut(PAR0+1, AppConfig.MyMACAddr.v[1]);
NICPut(PAR0+2, AppConfig.MyMACAddr.v[2]);
NICPut(PAR0+3, AppConfig.MyMACAddr.v[3]);
NICPut(PAR0+4, AppConfig.MyMACAddr.v[4]);
NICPut(PAR0+5, AppConfig.MyMACAddr.v[5]);
// Initialize Multicast registers
for ( i = 0; i < 8; i++ )
NICPut(MAR0+i, 0xff);
// Initialize CURRent pointer
NICPut(CURRP, RXSTART);
// Remember current receive page
NICReadPtr = RXSTART;
// Page 0, Abort Remote DMA and Activate the transmitter.
NICPut(CMDR, 0x22);
// Set Normal Mode
NICPut(TCR, 0x00);
}
}
BOOL MACIsTxReady(BOOL HighPriority)
{
// NICCurrentTxBuffer always points to free buffer, if there is any.
// If there is none, NICCurrentTxBuffer will be a in 'Use' state.
//return TxBuffers[NICCurrentTxBuffer].bFree;
// Check to see if previous transmission was successful or not.
return !(NICGet(CMDR) & 0x04);
}
BUFFER MACGetTxBuffer(BOOL HighPriority)
{
return 0;
}
void MACPut(BYTE val)
{
NICPut(RBCR0, 1);
NICPut(RBCR1, 0);
NICPut(CMDR, 0x12);
NICPut(NIC_DATAPORT, val);
}
void MACPutArray(BYTE *val, WORD len)
{
WORD_VAL t;
t.Val = len + (len & 1);
NICPut(ISR, 0x40);
NICPut(RBCR0, t.v[0]);
NICPut(RBCR1, t.v[1]);
NICPut(CMDR, 0x12);
//while ( len-- > 0 )
while( t.Val-- > 0 )
NICPut(NIC_DATAPORT, *val++);
// Make sure that DMA is complete.
#if 0
len = 255;
while( len && (NICGet(ISR) & 0x40) == 0 )
len--;
#endif
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -