dvi_hdmi.c.070605.int

linux下面的hdmi驱动

/*****************************************
 Copyright @ 2001-2004
 Sigma Designs, Inc. All Rights Reserved
 Proprietary and Confidential
 *****************************************/
/**
  @file   dvi_hdmi.c
  @brief  DVI and HDMI EIA 861C implementation
  
  @author Jacques Mahe, Christian Wolff
  @date   2004-07-28
*/

#define FORCE_HDMI
#define EDID_WORKAROUND

// to enable or disable the debug messages of this source file, put 1 or 0 below
#if 1
#define LOCALDBG ENABLE
#else
#define LOCALDBG DISABLE
#endif

// to enable or disable the debug messages for high-level I2C transfers, put 1 or 0 below
#if 0
#define I2CDBG ENABLE
#else
#define I2CDBG DISABLE
#endif

// To enable the displaying of all occurring interrups in the SiI9030, define the following symbol:
//#define DEBUG_HDMI_INTR 1
#undef DEBUG_HDMI_INTR

// Define this to test SRMs signed with the "facsimile" key, for debugging
//#define HDCP_USE_FACSIMILE_KEY

#include "sample_os.h"
#define ALLOW_OS_CODE 1

#include "../rua/include/rua.h"
#include "../rua/include/rua_property.h"
#include "../dcc/include/dcc.h"
#include "../rmcore/include/rmstatustostring.h"
#include "../rmlibcw/include/rmtime.h"

#include "dvi_hdmi.h"

// TODO implemet own SHA1 function, this one came from the PuTTY SSH client
#include "dss_sha.h"

extern RMascii *TVFormatString[];

// Uncomment GPIO_RESET to allow RESET of the SiI chip using a GPIO (here 4)
// ******************************* BEWARE ***********************************
// *** GPIO are layout specific. Most boards do not have a GPIO for reset ***
// *** Such GPIO, although MANDATORY to reset the SiI170 once HDCP has    ***
// *** been activated (No software reset on SiI170), may not be present   ***
// *** and defining GPIO_RESET to a value may cause unpredictible         ***
// *** result such as a SHORT (may damage). On an Odyssey board, this     ***
// *** may reset the PC!!!! Please review layout before enabling it.      ***
// *** Note: SiI9030 has a software reset and do not require any GPIO.    ***
#if ( (EM86XX_CHIP==EM86XX_CHIPID_TANGO2) || (EM86XX_CHIP==EM86XX_CHIPID_TANGO15) )
#define GPIO_RESET 4  // always define for tango2 boards
#else  
//#define GPIO_RESET 4
#endif

#define HOTPLUG_GUARD_TIME 2  // Guard delay for reporting changes after HotPlug low-to-high transition, in seconds
#define MAX_HDCP_ATTEMPTS 2 // Allow 2 chances as defined by spec.
#define MAX_I2C_ATTEMPTS 5
#define MAX_EDID_ATTEMPTS 2
#define HDCP_GUARD_TIME 800  // minimum time, in mSec, between TMDS on and HDCP auth, or between HDCP checks.

// Put 1 here until we have implemented the interrupt-driver I2C burst write
#define DISABLE_I2C_BURST_WRITE 1

#define HDCPRX_SLV              0x74
#define HDCP_CTRL_ADDR          0x0F
#define MASTER_CMD_ABORT        0x0F
#define MASTER_CMD_CLEAR_FIFO   0x09
#define MASTER_CMD_SEQ_RD       0x02
#define MASTER_CMD_ENHANCED_RD  0x04
#define MASTER_CMD_SEQ_WR       0x06
#define MDDC_FIFO_ADDR          0xF4
#define MAX_DDC_XFER 1023 // DDC size transfers
#define MAX_DDC_FIFO 16 // DDC FIFO size for transfers
#define DDC_TIMEOUT  100000 // 0.1 sec, in uSec
#define REPEATER_TIMEOUT  5000000 // 5 sec, in uSec
#define RI_128_THRESHOLD 127 // 0..127, phase in 128 frame HDCP cycle where Ri's will be compared

#define INFO_FRAME_AVI_ENABLE           0x0003
#define INFO_FRAME_SPD_ENABLE           0x000C
#define INFO_FRAME_AUD_ENABLE           0x0030
#define INFO_FRAME_MPG_ENABLE           0x00C0
#define INFO_FRAME_GEN_ENABLE           0x0300
#define INFO_FRAME_CP_ENABLE            0x0C00
#define INFO_FRAME_CP_ONCE              0x0800
#define INFO_FRAME_GEN2_ENABLE          0x3000

#define EDID_BLOCKS 8  // how many EDID blocks to hold in pDH
#define EDID_SIZE 128

#define SRM_SIZE 5 * 1024

// Assure pDH parameter is initialized
#define CHECK_pDH(func) do { \
	if (0) fprintf(stderr, "[HDMI] Call to " func "()\n"); \
	if (pDH == NULL) { \
		if (! manutest) fprintf(stderr, "[HDMI] Call to " func " with invalid DH structure!\n"); \
		return RM_FATALINVALIDPOINTER; \
	} \
} while (0)

// Check a certain pointer parameter, return error if NULL
#define CHECK_PTR(func, ptr) do { \
	if ((ptr) == NULL) { \
		if (! manutest) fprintf(stderr, "[HDMI] Call to " func " with invalid Data pointer!\n"); \
		return RM_FATALINVALIDPOINTER; \
	} \
} while (0)

struct DH_I2C {
	RMuint32 I2C;
	struct I2C_DeviceParams_type dev;
};

struct DH_control {
	struct RUA *pRUA;
	enum DH_vendor_parts part;
	RMuint32 i2c_module;
	struct DH_I2C i2c_tx;   // Transmitter (siI164, siI170 or siI9030)
	struct DH_I2C i2c_rx;   // Receiver (The monitor)
	struct DH_I2C i2c_tx2;  // Transmitter 2nd address
	enum DH_device_state state;            // State of the DVI/HDMI connector
	enum DH_connection cable;              // Are we connected? (Used for Hot Plug Detect)
	RMuint8 gpio_reset;
	RMuint32 info_frame_enable;             // See INFO_FRAME_xxxx flags
	RMuint32 VideoPixelClock;
	RMuint32 AudioSampleClock;
	struct dss_key SRM_dss;
	RMuint8 SRM[SRM_SIZE];
	RMuint32 SRM_Size;
	RMbool CPDesired;
	RMbool HDMI_mode;
	RMbool HDMI_audio;
	enum DCCRoute route;
	enum DH_EDID_select EDID_select;
	RMuint32 EDID_selection;  // force mode to this entry from EDID short descriptor list, when EDID_select == DH_EDID_force
	RMuint32 EDID_vfreq;  // preferred vsync frequency (50, 59, 60 etc.)
	RMuint32 EDID_hsize;  // preferred horizontal active size
	RMuint32 EDID_vsize;  // preferred vertical active size
	RMbool EDID_intl;     // preferred interlaced (TRUE) / progressive (FALSE) mode
	RMuint64 EDID_force_mask;  // try these VICs first (bit 1 = VIC 1, bit 2 = VIC 2 etc.)
	RMuint64 EDID_exclude_mask; // never use these VICs
	RMuint32 EDID_max_pixclk;
	RMuint32 EDID_min_pixclk;
	RMuint32 EDID_max_hfreq;
	RMuint32 EDID_min_hfreq;
	RMuint32 EDID_max_vfreq;
	RMuint32 EDID_min_vfreq;
	RMbool RxPresent;     // True if a Rx signal has ever been detected on this connector
	RMbool RxLost;        // True if Rx signal went down while hot plug active
	RMuint64 RepeaterTimeout;
	RMuint32 AudioHeader;
	RMuint64 HotPlugLastCheck;
	RMuint64 IntegrityLastCheck;
	RMbool Mute;
	RMuint32 TMDS_Threshold;
	enum GPIOId_type TMDS_GPIO;
	struct DH_HDMI_state HDMIState;
	RMbool HotPlugChanged;      // hardware state: HotPlug state has changed
	RMbool HotPlugState;        // hardware state: current HotPlug state
	RMbool HotPlugGuarded;
    RMbool ReceiverChanged  ;
	RMuint64 HotPlugGuardTime;
	RMuint8 EDID[EDID_BLOCKS][EDID_SIZE];
	RMuint32 EDID_blocks;
	RMbool CheckClock;  // TRUE if input clock stability is polled by DHCheckHDMI()
	RMbool ForceCTS;
	RMuint8 audio_mode;
	RMbool GuardTMDS;  // if TRUE, prevent TMDS from being turned on until PStable
	RMbool RequestTMDS;  // if TRUE, app would like to enable TMDS after GuardTMDS = FALSE
	RMbool IgnoreStable;  // ignore p_stable between soft reset and TMDS enable
	RMbool ForceIntegrityCheck;  // if set, perform HDCP integrity chak as soon as possible
};

struct DH_part_info {
	RMuint8 i2c_transmitter_write_address;        // Read address always Write address + 1
	RMuint8 i2c_transmitter_delay_us;             // Parts require delays (in microseconds) for i2c protocol
	RMuint8 i2c_receiver_write_address;           // Read address always Write address + 1
	RMuint8 i2c_receiver_delay_us;                // Parts require delays (in microseconds) for i2c protocol
	RMuint8 vendor_id_sud_address;                // Vendor ID subaddress used for check part
	RMuint8 vendor_id[4];                         // Vendor ID that should be read
	RMascii *part_string;                         // The name of the part
};

// delay == 10 for max. 100kHz I2C frequency
static const struct DH_part_info part_info[] = {
	{ 0x70, 10, 0x74, 8, 0x00, { 0x01, 0x00, 0x06, 0x00 }, "siI164" }, // siI164 (no HDCP support)
	{ 0x70, 10, 0x74, 8, 0x00, { 0x01, 0x00, 0x08, 0x00 }, "siI170" }, // siI170 (HDCP support)
	{ 0x72, 10, 0x00, 8, 0x00, { 0x01, 0x00, 0x53, 0x92 }, "siI190" }, // siI9030 (HDCP support) - Receiver accessed through transmitter (rx i2c address is 0x00)
    // 2007/01/02 added by [e-mail] [CAT6611]
	{ 0x98, 10, 0x00, 8, 0x00, { 0x00, 0xCA, 0x11, 0x06 }, "cat6611" }  // siI9030 (HDCP support) - Receiver accessed through transmitter (rx i2c address is 0x00)
    //~[e-mail] 2007/01/02
};

#ifndef HDCP_USE_FACSIMILE_KEY
// The Digital Content Protection LLC public key
// This is the public key for production!
static const RMuint8 SRM_y[128] = {
	0xc7, 0x06, 0x00, 0x52, 0x6b, 0xa0, 0xb0, 0x86, 0x3a, 0x80, 0xfb, 0xe0, 0xa3, 0xac, 0xff, 0x0d, 
	0x4f, 0x0d, 0x76, 0x65, 0x8a, 0x17, 0x54, 0xa8, 0xe7, 0x65, 0x47, 0x55, 0xf1, 0x5b, 0xa7, 0x8d, 
	0x56, 0x95, 0x0e, 0x48, 0x65, 0x4f, 0x0b, 0xbd, 0xe1, 0x68, 0x04, 0xde, 0x1b, 0x54, 0x18, 0x74, 
	0xdb, 0x22, 0xe1, 0x4f, 0x03, 0x17, 0x04, 0xdb, 0x8d, 0x5c, 0xb2, 0xa4, 0x17, 0xc4, 0x56, 0x6c, 
	0x27, 0xba, 0x97, 0x3c, 0x43, 0xd8, 0x4e, 0x0d, 0xa2, 0xa7, 0x08, 0x56, 0xfe, 0x9e, 0xa4, 0x8d, 
	0x87, 0x25, 0x90, 0x38, 0xb1, 0x65, 0x53, 0xe6, 0x62, 0x43, 0x5f, 0xf7, 0xfd, 0x52, 0x06, 0xe2, 
	0x7b, 0xb7, 0xff, 0xbd, 0x88, 0x6c, 0x24, 0x10, 0x95, 0xc8, 0xdc, 0x8d, 0x66, 0xf6, 0x62, 0xcb, 
	0xd8, 0x8f, 0x9d, 0xf7, 0xe9, 0xb3, 0xfb, 0x83, 0x62, 0xa9, 0xf7, 0xfa, 0x36, 0xe5, 0x37, 0x99};
#else
// The "facsimile" public key (used to verify the attached facsimile SRMs)
// This public key MUST NOT be used in final commercial products!
static const RMuint8 SRM_y[128] = {
	0x73, 0xeb, 0x34, 0xbb, 0x29, 0x08, 0xd1, 0x18, 0x1b, 0xe2, 0x27, 0xdb, 0x64, 0x7f, 0x4f, 0xd3, 
	0xa0, 0x9d, 0xe5, 0x91, 0xb3, 0xc6, 0x67, 0xac, 0x99, 0x45, 0x0d, 0xf1, 0x30, 0x6c, 0xdd, 0x3b, 
	0xa5, 0x2a, 0xd7, 0x73, 0xca, 0xe7, 0xad, 0xc9, 0x65, 0xb4, 0xc0, 0x40, 0xed, 0x81, 0xda, 0x73, 
	0xad, 0x2f, 0x9f, 0xed, 0xea, 0x91, 0xe7, 0xb0, 0xe9, 0x1a, 0x3d, 0x30, 0x07, 0xa3, 0x4a, 0xd1, 
	0x61, 0x69, 0x7c, 0xe7, 0xbb, 0xee, 0x1c, 0x4e, 0xb2, 0x33, 0x95, 0x4f, 0xb5, 0x23, 0x68, 0xd0, 
	0x56, 0x3b, 0x05, 0xef, 0xb1, 0xf7, 0xca, 0x0c, 0x33, 0x75, 0x7b, 0x12, 0x88, 0x17, 0xd4, 0x94, 
	0x75, 0x95, 0x28, 0xce, 0x89, 0x61, 0xae, 0xb9, 0xb9, 0x5b, 0x18, 0x41, 0xa2, 0x33, 0x93, 0xa1, 
	0x6b, 0xd0, 0x72, 0xbc, 0x3e, 0x70, 0xa9, 0xdf, 0x83, 0x06, 0x8a, 0x13, 0x8a, 0xf8, 0xbb, 0x57};
#endif

// DSS Public Key - Prime Modulus
static const RMuint8 SRM_p[128] = {
	0xd3, 0xc3, 0xf5, 0xb2, 0xfd, 0x17, 0x61, 0xb7, 0x01, 0x8d, 0x75, 0xf7, 0x93, 0x43, 0x78, 0x6b, 
	0x17, 0x39, 0x5b, 0x35, 0x5a, 0x52, 0xc7, 0xb8, 0xa1, 0xa2, 0x4f, 0xc3, 0x6a, 0x70, 0x58, 0xff, 
	0x8e, 0x7f, 0xa1, 0x64, 0xf5, 0x00, 0xe0, 0xdc, 0xa0, 0xd2, 0x84, 0x82, 0x1d, 0x96, 0x9e, 0x4b, 
	0x4f, 0x34, 0xdc, 0x0c, 0xae, 0x7c, 0x76, 0x67, 0xb8, 0x44, 0xc7, 0x47, 0xd4, 0xc6, 0xb9, 0x83, 
	0xe5, 0x2b, 0xa7, 0x0e, 0x54, 0x47, 0xcf, 0x35, 0xf4, 0x04, 0xa0, 0xbc, 0xd1, 0x97, 0x4c, 0x3a, 
	0x10, 0x71, 0x55, 0x09, 0xb3, 0x72, 0x15, 0x30, 0xa7, 0x3f, 0x32, 0x07, 0xb9, 0x98, 0x20, 0x49, 
	0x5c, 0x7b, 0x9c, 0x14, 0x32, 0x75, 0x73, 0x3b, 0x02, 0x8a, 0x49, 0xfd, 0x96, 0x89, 0x19, 0x54, 
	0x2a, 0x39, 0x95, 0x1c, 0x46, 0xed, 0xc2, 0x11, 0x8c, 0x59, 0x80, 0x2b, 0xf3, 0x28, 0x75, 0x27};
// DSS Public Key - Prime Divisor
static const RMuint8 SRM_q[20] = {
	0xee, 0x8a, 0xf2, 0xce, 0x5e, 0x6d, 0xb5, 0x6a, 0xcd, 0x6d, 
	0x14, 0xe2, 0x97, 0xef, 0x3f, 0x4d, 0xf9, 0xc7, 0x08, 0xe7};
// DSS Public Key - Generator
static const RMuint8 SRM_g[128] = {
	0x92, 0xf8, 0x5d, 0x1b, 0x6a, 0x4d, 0x52, 0x13, 0x1a, 0xe4, 0x3e, 0x24, 0x45, 0xde, 0x1a, 0xb5, 
	0x02, 0xaf, 0xde, 0xac, 0xa9, 0xbe, 0xd7, 0x31, 0x5d, 0x56, 0xd7, 0x66, 0xcd, 0x27, 0x86, 0x11, 
	0x8f, 0x5d, 0xb1, 0x4a, 0xbd, 0xec, 0xa9, 0xd2, 0x51, 0x62, 0x97, 0x7d, 0xa8, 0x3e, 0xff, 0xa8, 
	0x8e, 0xed, 0xc6, 0xbf, 0xeb, 0x37, 0xe1, 0xa9, 0x0e, 0x29, 0xcd, 0x0c, 0xa0, 0x3d, 0x79, 0x9e, 
	0x92, 0xdd, 0x29, 0x45, 0xf7, 0x78, 0x58, 0x5f, 0xf7, 0xc8, 0x35, 0x64, 0x2c, 0x21, 0xba, 0x7f, 
	0xb1, 0xa0, 0xb6, 0xbe, 0x81, 0xc8, 0xa5, 0xe3, 0xc8, 0xab, 0x69, 0xb2, 0x1d, 0xa5, 0x42, 0x42, 
	0xc9, 0x8e, 0x9b, 0x8a, 0xab, 0x4a, 0x9d, 0xc2, 0x51, 0xfa, 0x7d, 0xac, 0x29, 0x21, 0x6f, 0xe8, 
	0xb9, 0x3f, 0x18, 0x5b, 0x2f, 0x67, 0x40, 0x5b, 0x69, 0x46, 0x24, 0x42, 0xc2, 0xba, 0x0b, 0xd9};

// TODO this needs to be a board dependent setting!
#if (EM86XX_MODE == EM86XX_MODEID_WITHHOST)
#define TRANSMITTER_GPIO_CLOCK 2 // All odyssey boards use GPIO 0 and 1 for i2c, 2 and 3 for DDC line
#define TRANSMITTER_GPIO_DATA 3
#else
#define TRANSMITTER_GPIO_CLOCK 0 // All DVD player reference boards use same i2c lines for DDC and I2C
#define TRANSMITTER_GPIO_DATA 1
#endif

extern RMbool manutest;

struct DH_I2C *pi2c_prev_dev = NULL;
RMuint32 i2c_usage = 0;  // I2C mutex, two subsequent property calls are sometimes needed for one I2C access

static RMstatus DHReset_siI164(struct DH_control *pDH);
static RMstatus DHInitChip_siI164(struct DH_control *pDH);
static RMstatus DHEnableOutput_siI164(struct DH_control *pDH);
static RMstatus DHDisableOutput_siI164(struct DH_control *pDH);
static RMstatus DHGetAKSV_siI170(struct DH_control *pDH, RMuint8 *pAKSV);
static RMstatus DHGetBKSV_siI170(struct DH_control *pDH, RMuint8 *pBKSV);
static RMstatus DHGetAKSV_siI9030(struct DH_control *pDH, RMuint8 *pAKSV);
static RMstatus DHGetBKSV_siI9030(struct DH_control *pDH, RMuint8 *pBKSV);
static RMstatus DHEnableEncryption_siI170(struct DH_control *pDH);
static RMstatus DHEnableEncryption(struct DH_control *pDH);
static RMstatus DHDisableEncryption_siI9030(struct DH_control *pDH);
static RMstatus DHDisableEncryption(struct DH_control *pDH);
static RMstatus DHVerifyIntegrity_siI170(struct DH_control *pDH, RMbool check_hdcp);
static RMstatus DHAuthenticate_siI170(struct DH_control *pDH);
static RMstatus DHVerifyIntegrity_siI9030(struct DH_control *pDH, RMbool check_hdcp);
static RMstatus DHAuthenticate_siI9030(struct DH_control *pDH);
static RMbool DHCheckSignature(struct dss_key *dss, RMuint8 *sig, RMuint32 siglen, RMuint8 *data, RMuint32 datalen);

// cat6611 interrupt register definition.
#define HDMI_PKG_TYPE_NULL 0x00
#define HDMI_PKG_TYPE_ACP 0x04
#define HDMI_PKG_TYPE_ISRC1 0x05
#define HDMI_PKG_TYPE_ISRC2 0x06

#define REG_SW_RST       0x04
    #define B_ENTEST    (1<<7)
    #define B_REF_RST (1<<5)
    #define B_AREF_RST (1<<4)
    #define B_VID_RST (1<<3)
    #define B_AUD_RST (1<<2)
    #define B_HDMI_RST (1<<1)
    #define B_HDCP_RST (1<<0)
    
#define REG_INT_CTRL 0x05
    #define B_INTPOL_ACTL 0
    #define B_INTPOL_ACTH (1<<7)
    #define B_INT_PUSHPULL 0
    #define B_INT_OPENDRAIN (1<<6)

#define REG_INT_STAT1    0x06
    #define B_INT_AUD_OVERFLOW  (1<<7)
    #define B_INT_ROMACQ_NOACK  (1<<6)
    #define B_INT_RDDC_NOACK    (1<<5)
    #define B_INT_DDCFIFO_ERR   (1<<4)
    #define B_INT_ROMACQ_BUS_HANG   (1<<3)
    #define B_INT_DDC_BUS_HANG  (1<<2)
    #define B_INT_RX_SENSE  (1<<1)
    #define B_INT_HPD_PLUG  (1<<0)

#define REG_INT_STAT2    0x07
    #define B_INT_PKTISRC2  (1<<7)
    #define B_INT_PKTISRC1  (1<<6)
    #define B_INT_PKTACP    (1<<5)
    #define B_INT_PKTNULL  (1<<4)
    #define B_INT_PKTGENERAL   (1<<3)
    #define B_INT_KSVLIST_CHK   (1<<2)
    #define B_INT_AUTH_DONE (1<<1)
    #define B_INT_AUTH_FAIL (1<<0)

#define REG_INT_STAT3    0x08
    #define B_INT_AUD_CTS   (1<<6)
    #define B_INT_VSYNC     (1<<5)
    #define B_INT_VIDSTABLE (1<<4)
    #define B_INT_PKTMPG    (1<<3)
    #define B_INT_PKTSPD    (1<<2)
    #define B_INT_PKTAUD    (1<<1)
    #define B_INT_PKTAVI    (1<<0)

#define REG_INT_MASK1    0x09
    #define B_AUDIO_OVFLW_MASK (1<<7)
    #define B_DDC_NOACK_MASK (1<<5)
    #define B_DDC_FIFO_ERR_MASK (1<<4)
    #define B_DDC_BUS_HANG_MASK (1<<2)