📄 mb90560.h
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/* FFMC-16 IO-MAP HEADER FILE */
/* ========================== */
/* SOFTUNE WORKBENCH FORMAT */
/* C-DEFINITIONS FOR IO-SYMBOLS */
/* CREATED BY IO-WIZARD V2.16 */
/* Id: mb90560.h,v 4.3 2003/08/29 12:36:27 dfisch Exp $ */
/* */
/* *********************************************************** */
/* FUJITSU MIKROELEKTRONIK GMBH */
/* Am Siebenstein 6-10, 63303 Dreieich */
/* Tel.:++49/6103/690-0,Fax - 122 */
/* */
/* The following software is for demonstration purposes only. */
/* It is not fully tested, nor validated in order to fullfill */
/* its task under all circumstances. Therefore, this software */
/* or any part of it must only be used in an evaluation */
/* laboratory environment. */
/* This software is subject to the rules of our standard */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD */
/* "Micros Documentation & Software V3.0" see "\START.HTM" or */
/* see our Internet Page - */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html */
/* *********************************************************** */
/* ---------------------------------------------------------------------- */
/* Id: mb90560.iow,v 4.0 2003/05/07 15:27:09 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* History: */
/* Date Version Author Description */
/* 26-01-99 : initial creation */
/* 20.03.99 : wrong io adresses created due to error in IOWizard input file */
/* a special section was defined for the patch function register */
/* which lead to complete wrong IO adress map */
/* -> IOBASE section added for IO section generation, Patch section removed */
/* */
/* 29.03.99 : PPGC01, PPGC23, PPGC45 added to be able to start two PPGs simultaneously, */
/* additional bit names are modified according to PPG which is used */
/* Modified bit names in PCS01, PCS23, PCS45 according to PPG which is used */
/* */
/* 14.04.00 v1.3 JRO */
/* - generation of header and c file with IO-Wizard V 1.9 */
/* */
/* 30.04.99 V1.4 VSA */
/* - Bitdefinitions for parallelports are changed to Pxx, Dxx */
/* - 082h TMCSR0 -> TMCR0 */
/* - 086h TMCSR1 -> TMCR1 */
/* */
/* 18.05.99 V1.5 VSA */
/* - disclaimer added */
/* 02.08.99 V1.6 VSA */
/* - TMCSRx are added as double identifiers for TMCRx */
/* 27.08.99 V1.7 VSA */
/* - ICS23 Addr changed from 0069h to 006Ah */
/* */
/* 01.09.99 V1.8 MST */
/* - PPGCx change bit name, same bitname will be used for all channels */
/* - PCSx change bit name, same bitname will be used for all channels */
/* 30.11.99 V1.9 VSA */
/* - 0036 ADCR 2 D0 .. D9 added */
/* 13.04.00 V1.10 VSA */
/* - Security section is moved to the end of file */
/* 03.07.00 V1.11 VSA */
/* - ADC unit included (adc_01.h) */
/* 10.10.00 V2.0 MST */
/* - second Security2 section added at the beginning of the flash */
/* 01.11.00 V2.10 NMP */
/* - ADC structure realignment */
/* 08.11.00 V2.11 NMP */
/* - Rebuild to remove incorrect comments */
/* 23.07.02 V2.12 HWe new adc_01.h, icr.h (RMW-Problem) */
/* 30.01.03 V2.13 HWE longwordaccess to PPG Reload: PRL01, .. , PRL45 */
/* Id: mb90560.iow,v 4.0 2003/05/07 15:27:09 dfisch Exp */
/* - CVS and make controlled, specific security includefile */
/* ---------------------------------------------------------------------- */
/* Id: adc_01.h,v 2.2 2003/08/19 09:46:21 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* DESCRIPTION: Interrupt Control Register Declaration */
/* */
/* AUTHOR: Fujitsu Mikroelektronik GmbH */
/* */
/* HISTORY: */
/* Version 1.0 03.07.00 : original version */
/* 1.1 01.11.00 : Structure alignment */
/* Version 1.2 22.07.2002 : HW ADCS0, ADCR-Bitdefinitions as const, no RMV allowed */
/* Id: adc_01.h,v 2.0 2003/05/06 13:59:57 dfisch Exp */
/* - CVS and make controlled */
/* Id: adc_01.h,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* - adapted to BITFIELD_ORDER_MSB */
/* Id: adc_01.h,v 2.2 2003/08/19 09:46:21 dfisch Exp */
/* - ADCS1 Bit-defs as const, only Byte-write */
/* ---------------------------------------------------------------------- */
/* Id: ICR.H,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* */
/* DESCRIPTION: Interrupt Control Register Declaration */
/* */
/* AUTHOR: Fujitsu Mikroelektronik GmbH */
/* */
/* HISTORY: */
/* Version 1.0 26.01.99: */
/* - original version */
/* Version 1.2 11.02.99 */
/* - "extern" changed to pre-defined macro of IO-Wizard */
/* (__IO_EXTERN), requires IO-Wizard 1.7 or later */
/* */
/* Version 1.3 17.07.2002 HW Bitdefinitions as const, no RMV allowed */
/* Id: ICR.H,v 2.0 2003/05/06 09:03:53 dfisch Exp */
/* - CVS and make controlled */
/* Id: ICR.H,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* - adapted to BITFIELD_ORDER_MSB */
/* ---------------------------------------------------------------------- */
/* Id: security_mb90560.asm,v 1.2 2003/08/29 12:36:12 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* Id: security_mb90560.asm,v 1.1 2003/05/07 14:50:48 dfisch Exp */
/* - CVS and make controlled */
/* Id: security_mb90560.asm,v 1.2 2003/08/29 12:36:12 dfisch Exp */
/* - new families added */
/* - Security DISABLED/ENABLED prepared */
#ifndef __MB90XXX_H
# define __MB90XXX_H
/*
- Please define __IO_NEAR in LARGE and COMPACT memory model, if the default
data bank (DTB) is 00. This will result in better performance in these
models.
- Please define __IO_FAR in SMALL and MEDIUM memory model, if the default
data bank (DTB) is other than 00. This might be the case in systems with
external RAM, which are not using internal RAM as default data area.
- Please define neither __IO_NEAR nor __IO_FAR in all other cases. This
will work with almost all configurations.
*/
# ifdef __IO_NEAR
# ifdef __IO_FAR
# error __IO_NEAR and __IO_FAR must not be defined at the same time
# else
# define ___IOWIDTH __near
# endif
# else
# ifdef __IO_FAR
# define ___IOWIDTH __far
# else /* specified by memory model */
# define ___IOWIDTH
# endif
# endif
# ifdef __IO_DEFINE
# define __IO_EXTERN
# define __IO_EXTENDED volatile ___IOWIDTH
# else
# define __IO_EXTERN extern /* for data, which can have __io */
# define __IO_EXTENDED extern volatile ___IOWIDTH
# endif
typedef unsigned char IO_BYTE;
typedef unsigned short IO_WORD;
typedef unsigned long IO_LWORD;
typedef const unsigned short IO_WORD_READ;
/* REGISTER BIT STRUCTURES */
typedef union{ /* PORT DATA */
IO_BYTE byte;
struct{
IO_BYTE _P00 :1;
IO_BYTE _P01 :1;
IO_BYTE _P02 :1;
IO_BYTE _P03 :1;
IO_BYTE _P04 :1;
IO_BYTE _P05 :1;
IO_BYTE _P06 :1;
IO_BYTE _P07 :1;
}bit;
}PDR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _P10 :1;
IO_BYTE _P11 :1;
IO_BYTE _P12 :1;
IO_BYTE _P13 :1;
IO_BYTE _P14 :1;
IO_BYTE _P15 :1;
IO_BYTE _P16 :1;
IO_BYTE _P17 :1;
}bit;
}PDR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _P20 :1;
IO_BYTE _P21 :1;
IO_BYTE _P22 :1;
IO_BYTE _P23 :1;
IO_BYTE _P24 :1;
IO_BYTE _P25 :1;
IO_BYTE _P26 :1;
IO_BYTE _P27 :1;
}bit;
}PDR2STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _P30 :1;
IO_BYTE _P31 :1;
IO_BYTE _P32 :1;
IO_BYTE _P33 :1;
IO_BYTE _P34 :1;
IO_BYTE _P35 :1;
IO_BYTE _P36 :1;
IO_BYTE _P37 :1;
}bit;
}PDR3STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _P40 :1;
IO_BYTE _P41 :1;
IO_BYTE _P42 :1;
IO_BYTE _P43 :1;
IO_BYTE _P44 :1;
IO_BYTE _P45 :1;
IO_BYTE _P46 :1;
IO_BYTE _P47 :1;
}bit;
}PDR4STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _P50 :1;
IO_BYTE _P51 :1;
IO_BYTE _P52 :1;
IO_BYTE _P53 :1;
IO_BYTE _P54 :1;
IO_BYTE _P55 :1;
IO_BYTE _P56 :1;
IO_BYTE _P57 :1;
}bit;
}PDR5STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _P60 :1;
IO_BYTE _P61 :1;
IO_BYTE _P62 :1;
IO_BYTE _P63 :1;
IO_BYTE _P64 :1;
IO_BYTE _P65 :1;
IO_BYTE _P66 :1;
IO_BYTE _P67 :1;
}bit;
}PDR6STR;
typedef union{ /* PORT DIR */
IO_BYTE byte;
struct{
IO_BYTE _D00 :1;
IO_BYTE _D01 :1;
IO_BYTE _D02 :1;
IO_BYTE _D03 :1;
IO_BYTE _D04 :1;
IO_BYTE _D05 :1;
IO_BYTE _D06 :1;
IO_BYTE _D07 :1;
}bit;
}DDR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _D10 :1;
IO_BYTE _D11 :1;
IO_BYTE _D12 :1;
IO_BYTE _D13 :1;
IO_BYTE _D14 :1;
IO_BYTE _D15 :1;
IO_BYTE _D16 :1;
IO_BYTE _D17 :1;
}bit;
}DDR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _D20 :1;
IO_BYTE _D21 :1;
IO_BYTE _D22 :1;
IO_BYTE _D23 :1;
IO_BYTE _D24 :1;
IO_BYTE _D25 :1;
IO_BYTE _D26 :1;
IO_BYTE _D27 :1;
}bit;
}DDR2STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _D30 :1;
IO_BYTE _D31 :1;
IO_BYTE _D32 :1;
IO_BYTE _D33 :1;
IO_BYTE _D34 :1;
IO_BYTE _D35 :1;
IO_BYTE _D36 :1;
IO_BYTE _D37 :1;
}bit;
}DDR3STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _D40 :1;
IO_BYTE _D41 :1;
IO_BYTE _D42 :1;
IO_BYTE _D43 :1;
IO_BYTE _D44 :1;
IO_BYTE _D45 :1;
IO_BYTE _D46 :1;
IO_BYTE _D47 :1;
}bit;
}DDR4STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _D50 :1;
IO_BYTE _D51 :1;
IO_BYTE _D52 :1;
IO_BYTE _D53 :1;
IO_BYTE _D54 :1;
IO_BYTE _D55 :1;
IO_BYTE _D56 :1;
IO_BYTE _D57 :1;
}bit;
}DDR5STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _D60 :1;
IO_BYTE _D61 :1;
IO_BYTE _D62 :1;
IO_BYTE _D63 :1;
IO_BYTE _D64 :1;
IO_BYTE _D65 :1;
IO_BYTE _D66 :1;
IO_BYTE _D67 :1;
}bit;
}DDR6STR;
typedef union{ /* Analog Input Enable Register */
IO_BYTE byte;
struct{
IO_BYTE _AE0 :1;
IO_BYTE _AE1 :1;
IO_BYTE _AE2 :1;
IO_BYTE _AE3 :1;
IO_BYTE _AE4 :1;
IO_BYTE _AE5 :1;
IO_BYTE _AE6 :1;
IO_BYTE _AE7 :1;
}bit;
}ADERSTR;
typedef union{ /* UART0,1 */
IO_BYTE byte;
struct{
IO_BYTE _SOE :1;
IO_BYTE _SCKE :1;
IO_BYTE _BCH :1;
IO_BYTE _CS0 :1;
IO_BYTE _CS1 :1;
IO_BYTE _CS2 :1;
IO_BYTE _MD0 :1;
IO_BYTE _MD1 :1;
}bit;
struct{
IO_BYTE :3;
IO_BYTE _CS :3;
IO_BYTE _MD :2;
}bitc;
}SMR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _TXE :1;
IO_BYTE _RXE :1;
IO_BYTE _REC :1;
IO_BYTE _AD :1;
IO_BYTE _CL :1;
IO_BYTE _SBL :1;
IO_BYTE _P :1;
IO_BYTE _PEN :1;
}bit;
}SCR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
}bit;
}SIDR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _TIE :1;
IO_BYTE _RIE :1;
IO_BYTE _BDS :1;
IO_BYTE _TDRE :1;
IO_BYTE _RDRF :1;
IO_BYTE _FRE :1;
IO_BYTE _ORE :1;
IO_BYTE _PE :1;
}bit;
}SSR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _SOE :1;
IO_BYTE _SCKE :1;
IO_BYTE _BCH :1;
IO_BYTE _CS0 :1;
IO_BYTE _CS1 :1;
IO_BYTE _CS2 :1;
IO_BYTE _MD0 :1;
IO_BYTE _MD1 :1;
}bit;
struct{
IO_BYTE :3;
IO_BYTE _CS :3;
IO_BYTE _MD :2;
}bitc;
}SMR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _TXE :1;
IO_BYTE _RXE :1;
IO_BYTE _REC :1;
IO_BYTE _AD :1;
IO_BYTE _CL :1;
IO_BYTE _SBL :1;
IO_BYTE _P :1;
IO_BYTE _PEN :1;
}bit;
}SCR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
}bit;
}SIDR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE _TIE :1;
IO_BYTE _RIE :1;
IO_BYTE _BDS :1;
IO_BYTE _TDRE :1;
IO_BYTE _RDRF :1;
IO_BYTE _FRE :1;
IO_BYTE _ORE :1;
IO_BYTE _PE :1;
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