📄 mb90560.asm
字号:
/* FFMC-16 IO-MAP HEADER FILE */
/* ========================== */
/* CREATED BY IO-WIZARD V2.16 */
/* Id: mb90560.asm,v 4.3 2003/08/29 12:36:27 dfisch Exp $ */
/* */
/* *********************************************************** */
/* FUJITSU MIKROELEKTRONIK GMBH */
/* Am Siebenstein 6-10, 63303 Dreieich */
/* Tel.:++49/6103/690-0,Fax - 122 */
/* */
/* The following software is for demonstration purposes only. */
/* It is not fully tested, nor validated in order to fullfill */
/* its task under all circumstances. Therefore, this software */
/* or any part of it must only be used in an evaluation */
/* laboratory environment. */
/* This software is subject to the rules of our standard */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD */
/* "Micros Documentation & Software V3.0" see "\START.HTM" or */
/* see our Internet Page - */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html */
/* *********************************************************** */
/* ---------------------------------------------------------------------- */
/* Id: mb90560.iow,v 4.0 2003/05/07 15:27:09 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* History: */
/* Date Version Author Description */
/* 26-01-99 : initial creation */
/* 20.03.99 : wrong io adresses created due to error in IOWizard input file */
/* a special section was defined for the patch function register */
/* which lead to complete wrong IO adress map */
/* -> IOBASE section added for IO section generation, Patch section removed */
/* */
/* 29.03.99 : PPGC01, PPGC23, PPGC45 added to be able to start two PPGs simultaneously, */
/* additional bit names are modified according to PPG which is used */
/* Modified bit names in PCS01, PCS23, PCS45 according to PPG which is used */
/* */
/* 14.04.00 v1.3 JRO */
/* - generation of header and c file with IO-Wizard V 1.9 */
/* */
/* 30.04.99 V1.4 VSA */
/* - Bitdefinitions for parallelports are changed to Pxx, Dxx */
/* - 082h TMCSR0 -> TMCR0 */
/* - 086h TMCSR1 -> TMCR1 */
/* */
/* 18.05.99 V1.5 VSA */
/* - disclaimer added */
/* 02.08.99 V1.6 VSA */
/* - TMCSRx are added as double identifiers for TMCRx */
/* 27.08.99 V1.7 VSA */
/* - ICS23 Addr changed from 0069h to 006Ah */
/* */
/* 01.09.99 V1.8 MST */
/* - PPGCx change bit name, same bitname will be used for all channels */
/* - PCSx change bit name, same bitname will be used for all channels */
/* 30.11.99 V1.9 VSA */
/* - 0036 ADCR 2 D0 .. D9 added */
/* 13.04.00 V1.10 VSA */
/* - Security section is moved to the end of file */
/* 03.07.00 V1.11 VSA */
/* - ADC unit included (adc_01.h) */
/* 10.10.00 V2.0 MST */
/* - second Security2 section added at the beginning of the flash */
/* 01.11.00 V2.10 NMP */
/* - ADC structure realignment */
/* 08.11.00 V2.11 NMP */
/* - Rebuild to remove incorrect comments */
/* 23.07.02 V2.12 HWe new adc_01.h, icr.h (RMW-Problem) */
/* 30.01.03 V2.13 HWE longwordaccess to PPG Reload: PRL01, .. , PRL45 */
/* Id: mb90560.iow,v 4.0 2003/05/07 15:27:09 dfisch Exp */
/* - CVS and make controlled, specific security includefile */
/* ---------------------------------------------------------------------- */
/* Id: adc_01.h,v 2.2 2003/08/19 09:46:21 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* DESCRIPTION: Interrupt Control Register Declaration */
/* */
/* AUTHOR: Fujitsu Mikroelektronik GmbH */
/* */
/* HISTORY: */
/* Version 1.0 03.07.00 : original version */
/* 1.1 01.11.00 : Structure alignment */
/* Version 1.2 22.07.2002 : HW ADCS0, ADCR-Bitdefinitions as const, no RMV allowed */
/* Id: adc_01.h,v 2.0 2003/05/06 13:59:57 dfisch Exp */
/* - CVS and make controlled */
/* Id: adc_01.h,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* - adapted to BITFIELD_ORDER_MSB */
/* Id: adc_01.h,v 2.2 2003/08/19 09:46:21 dfisch Exp */
/* - ADCS1 Bit-defs as const, only Byte-write */
/* ---------------------------------------------------------------------- */
/* Id: ICR.H,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* */
/* DESCRIPTION: Interrupt Control Register Declaration */
/* */
/* AUTHOR: Fujitsu Mikroelektronik GmbH */
/* */
/* HISTORY: */
/* Version 1.0 26.01.99: */
/* - original version */
/* Version 1.2 11.02.99 */
/* - "extern" changed to pre-defined macro of IO-Wizard */
/* (__IO_EXTERN), requires IO-Wizard 1.7 or later */
/* */
/* Version 1.3 17.07.2002 HW Bitdefinitions as const, no RMV allowed */
/* Id: ICR.H,v 2.0 2003/05/06 09:03:53 dfisch Exp */
/* - CVS and make controlled */
/* Id: ICR.H,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* - adapted to BITFIELD_ORDER_MSB */
/* ---------------------------------------------------------------------- */
/* Id: security_mb90560.asm,v 1.2 2003/08/29 12:36:12 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* Id: security_mb90560.asm,v 1.1 2003/05/07 14:50:48 dfisch Exp */
/* - CVS and make controlled */
/* Id: security_mb90560.asm,v 1.2 2003/08/29 12:36:12 dfisch Exp */
/* - new families added */
/* - Security DISABLED/ENABLED prepared */
.PROGRAM MB90560
.TITLE MB90560
;------------------------
; IO-AREA DEFINITIONS :
;------------------------
.section IOBASE, IO, locate=0x0000 ; /* PORT DATA */
.GLOBAL __pdr0, __pdr1, __pdr2, __pdr3, __pdr4, __pdr5
.GLOBAL __pdr6, __ddr0, __ddr1, __ddr2, __ddr3, __ddr4
.GLOBAL __ddr5, __ddr6, __ader, __smr0, __scr0, __sidr0
.GLOBAL __sodr0, __ssr0, __smr1, __scr1, __sidr1, __sodr1
.GLOBAL __ssr1, __cdcr0, __cdcr1, __enir, __eirr, __elvr
.GLOBAL __adcs, __adcs0, __adcs1, __adcr, __adcr0, __adcr1
.GLOBAL __prl01, __prl0, __prll0, __prlh0, __prl1, __prll1
.GLOBAL __prlh1, __ppgc01, __ppgc0, __ppgc1, __pcs01, __prl23
.GLOBAL __prl2, __prll2, __prlh2, __prl3, __prll3, __prlh3
.GLOBAL __ppgc23, __ppgc2, __ppgc3, __pcs23, __prl45, __prl4
.GLOBAL __prll4, __prlh4, __prl5, __prll5, __prlh5, __ppgc45
.GLOBAL __ppgc4, __ppgc5, __pcs45, __tmrr0, __tmrr1, __tmrr2
.GLOBAL __dtcr0, __dtcr1, __dtcr2, __sigcr, __cpclr, __tcdt
.GLOBAL __tccs, __ipcp0, __ipcp1, __ipcp2, __ipcp3, __ics01
.GLOBAL __ics23, __romm, __occp0, __occp1, __occp2, __occp3
.GLOBAL __occp4, __occp5, __ocs0, __ocs2, __ocs4, __ocs1
.GLOBAL __ocs3, __ocs5, __tmcr0, __tmcsr0, __tmcr1, __tmcsr1
.GLOBAL __tmr0, __tmr0l, __tmr0h, __tmrlr0, __tmrlr0l, __tmrlr0h
.GLOBAL __tmr1, __tmr1l, __tmr1h, __tmrlr1, __tmrlr1l, __tmrlr1h
.GLOBAL __rdr0, __rdr1, __pacsr, __dirr, __lpmcr, __ckscr
.GLOBAL __wdtc, __tbtc, __fmcs, __icr, ___endio
__pdr0 .res.b 1 ;000000 /* PORT DATA */
PDR0 .equ 0x0000
__pdr1 .res.b 1 ;000001
PDR1 .equ 0x0001
__pdr2 .res.b 1 ;000002
PDR2 .equ 0x0002
__pdr3 .res.b 1 ;000003
PDR3 .equ 0x0003
__pdr4 .res.b 1 ;000004
PDR4 .equ 0x0004
__pdr5 .res.b 1 ;000005
PDR5 .equ 0x0005
__pdr6 .res.b 1 ;000006
PDR6 .equ 0x0006
.org 0x0010
__ddr0 .res.b 1 ;000010 /* PORT DIR */
DDR0 .equ 0x0010
__ddr1 .res.b 1 ;000011
DDR1 .equ 0x0011
__ddr2 .res.b 1 ;000012
DDR2 .equ 0x0012
__ddr3 .res.b 1 ;000013
DDR3 .equ 0x0013
__ddr4 .res.b 1 ;000014
DDR4 .equ 0x0014
__ddr5 .res.b 1 ;000015
DDR5 .equ 0x0015
__ddr6 .res.b 1 ;000016
DDR6 .equ 0x0016
__ader .res.b 1 ;000017 /* Analog Input Enable Register */
ADER .equ 0x0017
.org 0x0020
__smr0 .res.b 1 ;000020 /* UART0,1 */
SMR0 .equ 0x0020
__scr0 .res.b 1 ;000021
SCR0 .equ 0x0021
__sidr0 .res.b 1 ;000022
SIDR0 .equ 0x0022
.org 0x0022
__sodr0 .res.b 1 ;000022
SODR0 .equ 0x0022
__ssr0 .res.b 1 ;000023
SSR0 .equ 0x0023
__smr1 .res.b 1 ;000024
SMR1 .equ 0x0024
__scr1 .res.b 1 ;000025
SCR1 .equ 0x0025
__sidr1 .res.b 1 ;000026
SIDR1 .equ 0x0026
.org 0x0026
__sodr1 .res.b 1 ;000026
SODR1 .equ 0x0026
__ssr1 .res.b 1 ;000027
SSR1 .equ 0x0027
.org 0x0029
__cdcr0 .res.b 1 ;000029
CDCR0 .equ 0x0029
.org 0x002B
__cdcr1 .res.b 1 ;00002B
CDCR1 .equ 0x002B
.org 0x0030
__enir .res.b 1 ;000030 /* DTP, External Interrupts */
ENIR .equ 0x0030
__eirr .res.b 1 ;000031
EIRR .equ 0x0031
__elvr .res.b 2 ;000032
ELVR .equ 0x0032
__adcs .res.b 2 ;000034 /* AD Converter */
ADCS .equ 0x0034
.org 0x0034
__adcs0 .res.b 1 ;000034
ADCS0 .equ 0x0034
__adcs1 .res.b 1 ;000035
ADCS1 .equ 0x0035
__adcr .res.b 2 ;000036
ADCR .equ 0x0036
.org 0x0036
__adcr0 .res.b 1 ;000036
ADCR0 .equ 0x0036
__adcr1 .res.b 1 ;000037
ADCR1 .equ 0x0037
__prl01 .res.b 4 ;000038 /* Puls Pattern Generator Channel 0,1 */
PRL01 .equ 0x0038
.org 0x0038
__prl0 .res.b 2 ;000038
PRL0 .equ 0x0038
.org 0x0038
__prll0 .res.b 1 ;000038
PRLL0 .equ 0x0038
__prlh0 .res.b 1 ;000039
PRLH0 .equ 0x0039
__prl1 .res.b 2 ;00003A
PRL1 .equ 0x003A
.org 0x003A
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -