📄 ddpci2040.h
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#define PROGIF_OFFSET 9 // Prog
#define SUBCLASS_OFFSET 10 // Sub-class
#define BASECLASS_OFFSET 11 // Base-class
#define CACHELINESIZE_OFFSET 12 // Cache Line Size
#define LATENCYTIMER_OFFSET 13 // Latency Timer
#define HEADERTYPE_OFFSET 14 // Header Type
#define BIST_OFFSET 15 // BIST
#define HPICSRBAR_OFFSET 16 // HPI CSR Memory Base Addrress
#define CSPACEBAR_OFFSET 20 // Control Space Base Address
#define GPBBAR_OFFSET 24 // GPBus Base Address
#define SUBVENDORID_OFFSET 44 // Subsystem Vendor ID
#define SUBSYSID_OFFSET 46 // Subsystem ID
#define CAPPOINTER_OFFSET 52 // Capability Pointer
#define IRQLINE_OFFSET 60 // Interrupt Line
#define IRQPIN_OFFSET 61 // Interrupt Pin
#define MINGNT_OFFSET 62 // Min Grant
#define MAXLAT_OFFSET 63 // Max latency
#define GPBSELECT_OFFSET 68 // GPIO Select
#define GPBINDATA_OFFSET 69 // GPIO Input Data
#define GPBDATADIR_OFFSET 70 // GPIO Direction Control
#define GPBOUTDATA_OFFSET 71 // GPIO Output Data
#define GPBINTTYPE_OFFSET 72 // GPIO Interrupt Type
#define MISCCONTROL_OFFSET 76 // Misc Control
#define DIAG_OFFSET 79 // Diagnostic
#define PMCAPID_OFFSET 80 // PM Capability ID
#define PMNEXT_OFFSET 81 // PM Next-Item Pointer
#define PMCAP_OFFSET 82 // Power Management Capabilities
#define PMCNTLSTAT_OFFSET 84 // PM Control / Status
#define HPICSRIOBAR_OFFSET 88 // HPI CSR I/O Base Address
#define HSCAPID_OFFSET 92 // HS Capability ID
#define HSNEXT_OFFSET 93 // HS Next-Item Pointer
#define HSCSR_OFFSET 94 // HS_CSR
// Enum for writing and reading individual registers
typedef enum {
ENUM_VENDORID_OFFSET = VENDORID_OFFSET,
ENUM_DEVICEID_OFFSET = DEVICEID_OFFSET,
ENUM_COMMAND_OFFSET = COMMAND_OFFSET,
ENUM_STATUS_OFFSET = STATUS_OFFSET,
ENUM_REVISIONID_OFFSET = REVISIONID_OFFSET,
ENUM_PROGIF_OFFSET = PROGIF_OFFSET,
ENUM_SUBCLASS_OFFSET = SUBCLASS_OFFSET,
ENUM_BASECLASS_OFFSET = BASECLASS_OFFSET,
ENUM_CACHELINESIZE_OFFSET = CACHELINESIZE_OFFSET,
ENUM_LATENCYTIMER_OFFSET = LATENCYTIMER_OFFSET,
ENUM_HEADERTYPE_OFFSET = HEADERTYPE_OFFSET,
ENUM_BIST_OFFSET = BIST_OFFSET,
ENUM_HPICSRBAR_OFFSET = HPICSRBAR_OFFSET,
ENUM_CSPACEBAR_OFFSET = CSPACEBAR_OFFSET,
ENUM_GPBBAR_OFFSET = GPBBAR_OFFSET,
ENUM_SUBVENDORID_OFFSET = SUBVENDORID_OFFSET,
ENUM_SUBSYSID_OFFSET = SUBSYSID_OFFSET,
ENUM_CAPPOINTER_OFFSET = CAPPOINTER_OFFSET,
ENUM_IRQLINE_OFFSET = IRQLINE_OFFSET,
ENUM_IRQPIN_OFFSET = IRQPIN_OFFSET,
ENUM_MINGNT_OFFSET = MINGNT_OFFSET,
ENUM_MAXLAT_OFFSET = MAXLAT_OFFSET,
ENUM_GPBSELECT_OFFSET = GPBSELECT_OFFSET,
ENUM_GPBINDATA_OFFSET = GPBINDATA_OFFSET,
ENUM_GPBDATADIR_OFFSET = GPBDATADIR_OFFSET,
ENUM_GPBOUTDATA_OFFSET = GPBOUTDATA_OFFSET,
ENUM_GPBINTTYPE_OFFSET = GPBINTTYPE_OFFSET,
ENUM_MISCCONTROL_OFFSET = MISCCONTROL_OFFSET,
ENUM_DIAG_OFFSET = DIAG_OFFSET,
ENUM_PMCAPID_OFFSET = PMCAPID_OFFSET,
ENUM_PMNEXT_OFFSET = PMNEXT_OFFSET,
ENUM_PMCAP_OFFSET = PMCAP_OFFSET,
ENUM_PMCNTLSTAT_OFFSET = PMCNTLSTAT_OFFSET,
ENUM_HPICSRIOBAR_OFFSET = HPICSRIOBAR_OFFSET,
ENUM_HSCAPID_OFFSET = HSCAPID_OFFSET,
ENUM_HSNEXT_OFFSET = HSNEXT_OFFSET,
ENUM_HSCSR_OFFSET = HSCSR_OFFSET,
ENUM_INVALID = -1
} PCI2040_REG_OFFSETS, *PPCI2040_REG_OFFSETS;
#pragma pack(push)
#pragma pack(1)
// Structure used for HPI CSR Space
typedef struct _PCI2040_HPI_CSR {
ULONG IntEventSet;
ULONG IntEventClear;
ULONG IntMaskSet;
ULONG IntMaskClear;
USHORT HPIErrorReport;
USHORT Reserved1;
USHORT HPIResetRegister;
USHORT HPIImplementation;
USHORT HPIDataWidth;
USHORT Reserved2;
} PCI2040_HPI_CSR, *PPCI2040_HPI_CSR;
#pragma pack(pop)
// Definitions for IntEventSet and IntEventClear
#define INTDSP0 (1<<0) // Bit set if an interrupt has been generated by a device connected
// to the HPI[0] interface. Software can set this bit for diagnostics.
#define INTDSP1 (1<<1) // Bit set if an interrupt has been generated by a device connected
// to the HPI[1] interface. Software can set this bit for diagnostics.
#define INTDSP2 (1<<2) // Bit set if an interrupt has been generated by a device connected
// to the HPI[2] interface. Software can set this bit for diagnostics.
#define INTDSP3 (1<<3) // Bit set if an interrupt has been generated by a device connected
// to the HPI[3] interface. Software can set this bit for diagnostics.
#define GPINT (1<<26) // Bit set if an interrupt has been generated by a device connected
// to the GPINT# interface. Software can set this bit for diagnostics.
#define INTGPIO2 (1<<27) // Set when GPIO2Pin selects GPIO2 as an interrupt event input, and the
// event type selected by the GPIO Interrupt Event Type Register occurs.
#define INTGPIO3 (1<<28) // Set when GPIO3Pin selects GPIO3 as an interrupt event input, and the
// event type selected by the GPIO Interrupt Event Type Register occurs.
#define GPERROR (1<<29) // Bit set upon serious error conditions on the GP interface, and
// allows software to gracefully terminate communication with a GP device.
#define HPIERROR (1<<30) // Bit set upon serious error conditions on the HPI interface, and allows
// software to gracefully terminate communication with an HPI device.
// This bit is the OR combination of the HPI errors in the HPI Error Report
// Register.
// This macro is provided for retrieving HPI error detail
// using the IOCTL_PCI2040_GET_INTERRUPT_INFORMATION. The
// HPI error detail is returned starting at bit location 16
// and follows the order defined for the HPI Error fields.
#define GetHPIErrorDetail(a) ((a>>16)&0xF)
// Definitions for IntMaskSet and IntMaskClear
// 28:0 --- When set, interrupt will be generated when the corresponding interrupt
// event bit (See ABOVE) is set.
#define GPERRORMASK (1<<29) // When set, an interrupt will be generated when the IntEvent.GPError
// event bit is set. When set, the GP state machine will never cause target
// aborts on PCI and will return the PCI slave zeros on such errors. When
// set, errors on posted writes will not cause SERR# signal assertions
// enabled by SERR_EN. When this bit is cleared, target aborts may occur and
// SERR# may be signaled as a result of a posted write error.
#define HPIERRORMASK (1<<30) // When set, an interrupt will be generated when the IntEvent.HPIError event
// bit is set (See Table 34). When set, the HPI state machine will never cause
// target aborts on PCI and will return the PCI slave zeros on such errors.
// When set, errors on posted writes will not cause SERR# signal assertions
// enabled by SERR_EN. When this bit is cleared, target aborts may occur and
// SERR# may be signaled as a result of a posted write error.
#define MASTERINTENABLE (1<<31) // When set, external interrupts will be generated in accordance with the
// IntMask register. If clear, no external interrupts will be generated.
// Definitions for HPIErrorReport
#define HPIERR0 (1<<0) // Bit set if a serious error occurs on the HPI[0] interface.
#define HPIERR1 (1<<1) // Bit set if a serious error occurs on the HPI[1] interface.
#define HPIERR2 (1<<2) // Bit set if a serious error occurs on the HPI[2] interface.
#define HPIERR3 (1<<3) // Bit set if a serious error occurs on the HPI[3] interface.
// Definitions for HPIResetRegister
#define HPI0_RST (1<<0) // HPI Reset 0. When set, HRST0# is asserted.
#define HPI1_RST (1<<1) // HPI Reset 1. When set, HRST1# is asserted.
#define HPI2_RST (1<<2) // HPI Reset 2. When set, HRST2# is asserted.
#define HPI3_RST (1<<3) // HPI Reset 3. When set, HRST3# is asserted.
// Definitions for HPIImplementation
#define DSP_PRSNT0 (1<<0) // DSP0 Present. These bits indicate if the DSP0 is present on the HPI I/F.
#define DSP_PRSNT1 (1<<1) // DSP1 Present. These bits indicate if the DSP1 is present on the HPI I/F.
#define DSP_PRSNT2 (1<<2) // DSP2 Present. These bits indicate if the DSP2 is present on the HPI I/F.
#define DSP_PRSNT3 (1<<3) // DSP3 Present. These bits indicate if the DSP3 is present on the HPI I/F.
// Definitions for HPIDataWidth
#define DWIDTH0 (1<<0) // When set, the HPI[0] data bus is 16-bits (C6x). When zero, it is 8-bits (C54x).
#define DWIDTH1 (1<<1) // When set, the HPI[1] data bus is 16-bits (C6x). When zero, it is 8-bits (C54x).
#define DWIDTH2 (1<<2) // When set, the HPI[2] data bus is 16-bits (C6x). When zero, it is 8-bits (C54x).
#define DWIDTH3 (1<<3) // When set, the HPI[3] data bus is 16-bits (C6x). When zero, it is 8-bits (C54x).
// Structure used to write PCI register
typedef struct _PCI2040_WRITE_REG
{
PCI2040_REG_OFFSETS Regoff; // Register to read/write
ULONG DataVal; // Data to read/write
} PCI2040_WRITE_REG, *PPCI2040_WRITE_REG;
// Useful PCI Register value definitions
// PCI Control Register
#define PCIREG_CTL_FBBEN (1<<9) // Fast Back-to-Back Enable. This bit
// controls whether or not the device
// is allowed to perform back to back
// capability for bus master transaction.
// This bit is hardwired to 0 and indicates
// that FBB transfers are not supported
#define PCIREG_CTL_SERREN (1<<8) // System Error (SERR#) Enable. This bit
// is an enable for the output driver on
// the SERR# pin. If this bit is cleared,
// and a system error condition is set,
// the error signal will not appear on the
// external SERR# pin
#define PCIREG_CTL_STEPEN (1<<7) // Address/Data Stepping Control. This bit
// indicates whether or not the device
// performs address stepping. This bit is
// hard wired to "0"
#define PCIREG_CTL_PERREN (1<<6) // Parity Error Response Enable. This bit
// controls whether or not the device
// responds to detected parity errors.
// If this bit is set, the device will
// respond normally to parity errors.
// Otherwise, the device will ignore detected
// parity errors
#define PCIREG_CTL_VGAEN (1<<5) // VGA Palette Snoop. This bit is not applicable
// and is hardwired to a "0"
#define PCIREG_CTL_MWIEN (1<<4) // Memory Write and Invalidate Enable. This bit
// enables the device to use the Memory Write and
// Invalidate command. This device does not support
// MWI and uses MW instead. This bit is hardwired
// to "0"
#define PCIREG_CTL_Special (1<<3) // Special Cycle. This bit controls the device抯
// response to special cycle commands. This device
// does not monitor any special commands, this bit
// is set to "0"
#define PCIREG_CTL_MASTEN (1<<2) // Bus Master Control. This bit allows a PCI device
// to function as a bus master. This bit is hardwired
// to "0"
#define PCIREG_CTL_MEMEN (1<<1) // Memory Space Enable. This bit enables the device
// to respond to memory accesses to any of the
// defined base address memory regions. If this bit
// is cleared, the device will not respond to memory
// mapped accesses.
#define PCIREG_CTL_IOEN (1<<0) // I/O Space Control. This bit enables the device
// to respond to I/O accesses within it抯 defined
// base address register I/O regions
// HPI Control Register (HPIC) CSpaceaddr+0
// *** NOTE ***
// The following definitions are defined for the C54X DSP.
// If a version of this software is created for the C6X, then the definitions and use
// in the drivers need to be changed.
//
#define HPIC_BOB (1<<0|1<<8) // The byte-order-bit. This bit determines the placement
// for the two bytes of a transfer. If BOB=1, the
// first byte of a transfer is least significant. If
// BOB=0, the first byte is most significant. This bit
// can only be accessed (written or read) by the host,
// and it must be initialized before the first data or
// address register access.
#define HPIC_DSPINT (1<<2|1<<10) // The host-to-⌨️ 快捷键说明
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