ddpci2040.h

DSP（TI公司的5416)的实例程序

////////////////////////////////////////////////////////////////////
//     File:   ddpci2040.H
//
//     Purpose: This is the Public include file for the C54x EVM 
//              device drivers and client DLL.
//
//     Copyright (c) 1999, DNA Enterprises, Inc.
////////////////////////////////////////////////////////////////////
#ifndef _DDPCI2040_H
#define _DDPCI2040_H

        // Define IOCTL codes for driver access
#define PCI2040_DEVICE_TYPE    0x8001
#define PCI2040_FUNCTION_BASE  0x0800

#define PCI2040_MAKEIOCTL(n)\
    CTL_CODE((ULONG)PCI2040_DEVICE_TYPE, PCI2040_FUNCTION_BASE+(n), METHOD_BUFFERED, FILE_ANY_ACCESS)

        // Reset Driver and EVM Board
        // Input:  none
        // Output: none
#define IOCTL_PCI2040_DRIVER_RESET\
            PCI2040_MAKEIOCTL(0)

        // Dump PCI Configuration Registers
        // Input:  none
        // Output: PPCI2040_CONFIGURATION - pointer to structure containing
        //         the PCI configuration information
        // Notes:  this call reads the PCI configuration to the caller supplied buffer.
#define IOCTL_PCI2040_DUMP_CONFIGURATION\
            PCI2040_MAKEIOCTL(1)

        // Store PCI Configuration Registers
        // Input: PPCI2040_CONFIGURATION - pointer to structure containing
        //         the PCI configuration information
        // Output:  none
        // Notes:  this call writes the PCI configuration in the caller supplied buffer.
#define IOCTL_PCI2040_STORE_CONFIGURATION\
            PCI2040_MAKEIOCTL(2)

        // Read PCI Configuration Register
        // Input:  
        // Output:
#define IOCTL_PCI2040_READ_PCI_REG\
            PCI2040_MAKEIOCTL(3)

        // Write PCI Configuration Register
        // Input:
        // Output: none
#define IOCTL_PCI2040_WRITE_PCI_REG\
            PCI2040_MAKEIOCTL(4)

        // Map HPI CSR registers into user memory space
        // Input:  none
        // Output: PPCI2040_HPI_CSR_ADDRESSES - structure containing user-mapped 
        //         pointer to the mapped HPI CSR registers and number of bytes
        //         of mapped memory.
        // Notes:  the memory must be unmapped using
        //         IOCTL_PCI2040_UNMAP_HPI_CSR_SPACES,
        //         pointer is vaild only in the caller's address space.
        //         Only one active mapping of the HPI regs is allowed.
#define IOCTL_PCI2040_MAP_HPI_CSR_SPACES\
            PCI2040_MAKEIOCTL(5)

        // Unmap HPI CSR Registers from User's Memory Space
        // Input:  PPCI2040_HPI_CSR_ADDRESSES - pointer to the structure returned
        //         from IOCTL_PCI2040_MAP_HPI_CSR_SPACES
        // Output: none
        // Notes:  the structure must be the structure
        //         that was output by IOCTL_PCI2040_MAP_HPI_CSR_SPACES
#define IOCTL_PCI2040_UNMAP_HPI_CSR_SPACES\
            PCI2040_MAKEIOCTL(6)

        // Map DSP HPI Registers into User's Memory Space
        // Input:  none
        // Output: PPCI2040_DSP_HPI_ADDRESSES - structure containing user-mapped 
        //         pointer to the mapped DSP HPI mwmory and number of bytes
        //         of mapped memory.
        // Notes:  the memory must be unmapped using
        //         IOCTL_PCI2040_UNMAP_DSP_HPI_SPACES,
        //         pointer is vaild only in the caller's address space.
        //         Only one active mapping of the DSP HPI space is allowed.
#define IOCTL_PCI2040_MAP_DSP_HPI_SPACES\
            PCI2040_MAKEIOCTL(7)

        // Unmap DSP HPI Registers from User's Memory Space
        // Input:  PPCI2040_DSP_HPI_ADDRESSES - pointer to the structure returned
        //         from IOCTL_PCI2040_MAP_DSP_HPI_SPACES
        // Output: none
        // Notes:  the structure must be the structure
        //         that was output by IOCTL_PCI2040_MAP_DSP_HPI_SPACES
#define IOCTL_PCI2040_UNMAP_DSP_HPI_SPACES\
            PCI2040_MAKEIOCTL(8)

        // Map GP Bus (TBC) into User's Memory Space
        // Input:  
        // Output: 
        // Notes:  
#define IOCTL_PCI2040_MAP_GPB_TBC_SPACES\
            PCI2040_MAKEIOCTL(9)
    
        // Unmap GP Bus (TBC) from User's Memory Space
        // Input:  
        // Output: 
        // Notes:  
#define IOCTL_PCI2040_UNMAP_GPB_TBC_SPACES\
            PCI2040_MAKEIOCTL(10)

        // The following is used for the DSP reset IOCTLs
typedef enum {
    Select_DSP0 = 0,        // Selects DSP 0 as target
    Select_DSP1,            // "
    Select_DSP2,
    Select_DSP3
} DSPSelectEnum, *PDSPSelectEnum;

        // Hold DSP in Reset State
        // Input:  PDSPSelectEnum containing the number of the DSP to reset
        // Output: none
#define IOCTL_PCI2040_DSP_RESET_HOLD\
            PCI2040_MAKEIOCTL(11)

        // Release DSP from Reset State
        // Input:  PDSPSelectEnum containing the number of the DSP to reset
        // Output: none
#define IOCTL_PCI2040_DSP_RESET_RELEASE\
            PCI2040_MAKEIOCTL(12)

        // Reset Install RING3 interrupt event handle
        // Input:  Kernel32 mapped event handle
        // Output: none
        // Note:
#define IOCTL_PCI2040_INSTALL_INTERRUPT_EVENT\
            PCI2040_MAKEIOCTL(13)

        // Reset Clear RING3 interrupt event handle
        // Input:  none
        // Output: none
        // Note:
#define IOCTL_PCI2040_CLEAR_INTERRUPT_EVENT\
            PCI2040_MAKEIOCTL(14)

        // Get event information
        // Input:  none
        // Output: Event status
        // Note:  The returned status uses values defined for the HPI CSR
        //        control register and HPI ERROR detail that has been shifted
        //        16 bits to the left (see defines below).
#define IOCTL_PCI2040_GET_INTERRUPT_INFORMATION\
            PCI2040_MAKEIOCTL(15)

        // Wait in driver for interrupt signal (NT only)
        // Input:  none
        // Output: none
        // Note:   WinNT only
#define IOCTL_PCI2040_WAITFOR_PROCESSOR_SIGNAL\
            PCI2040_MAKEIOCTL(16)

        // Maximum number of unhandled interrupts the driver will
        // queue without the application servicing them.  Should
        // more than this number of interrupts occur, the driver
        // will discard the oldest interrupts as new ones come in.
#define MAX_UNHANDLED_INTERRUPTS    64

#define PCI2040_VENDOR_ID   0x104C
#define PCI2040_DEVICE_ID   0XAC60
#define MAX_PCI2040_BOARDS  8

#define HPICSR_SIZE         4096        // Size of HPICSR segment to map
#define HPI_MAPPED_DSP_SZ   1024        // Size of segment for each DSP
#define CSpace_SIZE         32768       // Size of Control Space segment to map
#define GPB_SIZE            256         // Size of General Purpose segment to map

#pragma pack(push)
#pragma pack(1)
        // Structure used to access the PCI configuration
typedef struct _PCI2040_CONFIGURATION {
    USHORT  VendorID;       // Vendor ID
    USHORT  DeviceID;       // Device ID
    USHORT  Command;        // Command
    USHORT  Status;         // Status
    UCHAR   RevisionID;     // Revision ID
    UCHAR   ProgIf;         // Prog
    UCHAR   SubClass;       // Sub-class
    UCHAR   BaseClass;      // Base-class
    UCHAR   CacheLineSize;  // Cache Line Size
    UCHAR   LatencyTimer;   // Latency Timer
    UCHAR   HeaderType;     // Header Type
    UCHAR   BIST;           // BIST
    ULONG   HPICSRBar;      // HPI CSR Memory Base Addrress
    ULONG   CSpaceBar;      // Control Space Base Address
    ULONG   GPBBar;         // GPBus Base Address
    ULONG   Reserve0[4];    // Reserved
    USHORT  SubVendorID;    // Subsystem Vendor ID
    USHORT  SubSysID;       // Subsystem ID
    ULONG   Reserve1;       // Reserved
    UCHAR   CapPointer;     // Capability Pointer
    UCHAR   Reserve2[3];    // Reserved
    ULONG   Reserve3;       // Reserved
    UCHAR   IRQLine;        // Interrupt Line
    UCHAR   IRQPin;         // Interrupt Pin
    UCHAR   MinGnt;         // Min Grant
    UCHAR   MaxLat;         // Max latency
    USHORT  Reserve4[2];    // Reserved
    UCHAR   GPBSelect;      // GPIO Select
    UCHAR   GPBInData;      // GPIO Input Data
    UCHAR   GPBDataDir;     // GPIO Direction Control
    UCHAR   GPBOutData;     // GPIO Output Data
    UCHAR   GPBIntType;     // GPIO Interrupt Type
    UCHAR   Reserve5[3];    // Reserved
    USHORT  MiscControl;    // Misc Control
    UCHAR   Reserve14;      // Reserved
    UCHAR   Diag;           // Diagnostic
    UCHAR   PMCapID;        // PM Capability ID
    UCHAR   PMNext;         // PM Next-Item Pointer
    USHORT  PMCap;          // Power Management Capabilities
    USHORT  PMCntlStat;     // PM Control / Status
    USHORT  Reserve6;       // Reserved
    ULONG   HPICSRIOBar;    // HPI CSR I/O Base Address
    UCHAR   HSCapID;        // HS Capability ID
    UCHAR   HSNext;         // HS Next-Item Pointer
    UCHAR   HSCSR;          // HS_CSR
    UCHAR   Reserve7[5];    // Reserved
} PCI2040_DUMP_CONFIG_REGS, *PPCI2040_DUMP_CONFIG_REGS;
#pragma pack(pop)

        // Defines for register numbers
#define VENDORID_OFFSET     0       // Vendor ID
#define DEVICEID_OFFSET     2       // Device ID
#define COMMAND_OFFSET      4       // Command
#define STATUS_OFFSET       6       // Status
#define REVISIONID_OFFSET   8       // Revision ID