rx-pcm.c

S3C2410例子程序

#include "def.h"
#include "2410lib.h"
#include "option.h"
#include "2410addr.h"
#include "interrupt.h"

#include "coff.h"
#include "hpi.h"

#define  BIT_CLR(X, bits)		(X &= ~bits)
#define  BIT_SET(X, bits)		(X |=  bits)
#define  PCLK		(FCLK/4)

void DMA2_Isr(void) __attribute__ ((interrupt("IRQ")));
		
unsigned short* pflag0 = (unsigned short*)(0x2000a000+4000*2);
unsigned short* pflag1 = (unsigned short*)(0x2000a000+4001*2);

//arm-elf-ld -r -o dsp.o -b binary exp-audio.out

/*
 
 PLL SETTINGS ->    FCLK        PCLK  
 
 86h, bh,0h | 131.076920|  32.769230|   4.000150|   0.000150
 86h, bh,1h |  65.538460|  16.384615|   2.000075|   0.000075
 cdh, bh,0h | 196.615387|  49.153847|   6.000225|   0.000225
 */	

//===================================================================
void DMA2_Isr(void)
{
    ClearPending(BIT_DMA2);     //Clear pending bit
}

//*********************[ Test_Iis ] *********************************
void Main(void)
{
    int  flag = 0;
    
    unsigned long size;
     
	extern unsigned long __input_coff;
	extern unsigned long __input_coff_end;
    
    ChangeClockDivider(1,1);        	// 1:2:4
    ChangeMPllValue(0xcd,0x0b,0x0);  	// FCLK=196.615387MHz (PCLK=49.153847MHz)
    Uart_Init(49153847, 115200);
    
    load_coff((unsigned long)(&__input_coff), (unsigned long)(&__input_coff_end));
	
    IIS_PortSetting();

    pISR_DMA2  = (unsigned)DMA2_Isr;

    Init1341(0);

    rDISRC2 = 0x2000a000;

    rDISRCC2 = (0<<1) + (0<<0);                 //The source is in the system bus(AHB), Increment      
    rDIDST2  = ((U32)IISFIFO);                  //IISFIFO    
    rDIDSTC2 = (1<<1) + (1<<0);                 //The destination is in the peripheral bus(APB), Fixed  
    
    // DSP FIXED
    size 	 = 8000;							// 
    rDCON2   = (1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(0<<24)+(1<<23)+(0<<22)+(1<<20)+(size/2);
    
    //1010 0000 1001 xxxx xxxx xxxx xxxx xxxx
    //Handshake[31], Sync PCLK[30], CURR_TC Interrupt Request[29], Single Tx[28], Single service[27], 
    //I2SSDO[26:24], DMA source selected[23],Auto-reload[22], Half-word[21:20], size/2[19:0]
      
    rDMASKTRIG2 = (0<<2) + (1<<1) + (0<<0);          //No-stop[2], DMA2 channel On[1], No-sw trigger[0] 
    
    rIISPSR = (23<<5) + 23;

    rIISCON = (1<<5) + (1<<2) + (1<<1);         //Tx DMA enable[5], Rx idle[2], Prescaler enable[1]
 
    //Master mode[8],Tx mode[7:6],Low for Left Channel[5],
	// IIS format[4],16bit ch.[3],CDCLK 256fs[2],IISCLK 32fs[1:0]
    rIISMOD = (0<<8) + (2<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);
    rIISFCON = (1<<15) + (1<<13);        //Tx DMA,Tx FIFO --> start piling....
    
    rIISCON |= 0x1; 
    
    BIT_CLR(rINTMSK, BIT_DMA2);
    
    while(1);
}