📄 idct.lst
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// PRAM offsets
0000 oDGFILT equ 0
0001 oPREFILT equ 1
0002 oPREFILT2 equ 2
0003 oFSGFILT equ 3
0004 oSH_GAIN equ 4
0005 oMED_GRN_THRESH equ 5
0006 oSH_CORE_THRESH equ 6
0007 oSH_CORE_DIV equ 7
0008 oRRCoeff equ 8
0009 oRGCoeff equ 9
000A oRBCoeff equ 10
000B oGRCoeff equ 11
000C oGGCoeff equ 12
000D oGBCoeff equ 13
000E oBRCoeff equ 14
000F oBGCoeff equ 15
0010 oBBCoeff equ 16
0011 oRtoY equ 17
0012 oRtoU equ 18
0013 oRtoV equ 19
0014 oGtoY equ 20
0015 oGtoU equ 21
0016 oGtoV equ 22
0017 oBtoY equ 23
0018 oBtoU equ 24
0019 oBtoV equ 25
001A oACGain equ 26
001E oI0Store equ 30
001F oI3Store0 equ 31
0020 oI3Store1 equ 32
0021 oS0Store equ 33
//DSPRAM offsets
0000 BAY_BLOCK equ 0
0400 YBLOCK equ (BAY_BLOCK+(32*32))
0600 UBLOCK equ (YBLOCK+512)
0800 VBLOCK equ (UBLOCK+512)
//VBLOCK equ (UBLOCK+128)
0A00 DCT_OUT_BUF equ (VBLOCK+512)
0D00 RL_OUT_BUF equ (DCT_OUT_BUF+(128*6))
1200 COPY_Y_BUFF equ 0x1200
0020 BAY_WIDTH equ 32
0021 BAY_WIDTH1 equ 33
1DC0 GAMMA_256 equ 0x1dc0
1F00 QTBL_0 equ 0x1f00
1F80 QTBL_1 equ 0x1f80
1EC0 ZZ_TABLE equ 0x1ec0
0080 PROG1_START equ 0x080
00A0 PROG2_START equ 0x0A0
00E0 DATA1_START equ 0xe0
00F0 DATA2_START equ 0xf0
00C0 PROG1I_START equ 0xc0
00D0 PROG2I_START equ 0xd0
0002 VLOOPCOUNT equ 2 // should be 2 for 320x240
0014 HLOOPCOUNT equ 20 // should be 20 for 320x240
// local variables
// based starting at 0x1800
1800 Y_DC_PRED equ 0x1800
1802 U_DC_PRED equ 0x1802
1804 V_DC_PRED equ 0x1804
// constants for DCT
22A2 K6c equ 8866 // ((sqrt(2) * cos(6*pi/16))* 16384)
539E K6s equ 21406 // ((sqrt(2) * sin(6*pi/16))* 16384)
AC62 nK6s equ -21406
4B41 K3c equ 19265 // ((sqrt(2) * cos(3*pi/16))* 16384)
3248 K3s equ 12872 // ((sqrt(2) * sin(3*pi/16))* 16384)
CDB8 nK3s equ -12872
58C5 K1c equ 22725 // ((sqrt(2) * cos(pi/16))* 16384)
11A8 K1s equ 4520 // ((sqrt(2) * sin(pi/16))* 16384)
EE58 nK1s equ -4520
2D41 S_5 equ 11585 // (sqrt(0.5) * 16384) */
main:
0000 000004820004 ldc s0,4 //input block is 16bytesX16bytes
0001 000004620010 ldc i3,16 //process row first
0002 000014920021 stc s0,#oS0STORE
0003 00001472001F stc i3,#oI3STORE0 //??
0004 000004020000 ldc i0,0 //only for development purpose, put input block at address 0
0005 000000800008 call idct
0006 000000000000 nopd
//nopd
0007 000000E00000 wait
//Register Usage
//r01:i0, j0 ,...
//r02:i1, j1 ,...
//r03:...
//r04:...
//r05:...
//r06:...
//r07:i7, j7 ,...
//r08: Not used
//r09: k6c, k3c,...
//r10: K6s, k3s,...
//r11: nK6s, nK3s,...
//r12: S_5
idct:
//**************************************************************************************************************
//* Parameters
//* i0: address of input block
//* #oS0STORE: Block width. s0=5 means block width 32 bytes (s0=4 means width 16 bytes).
//**************************************************************************************************************
0008 00000542000E ldc shft,14 // multiplier shift register
0009 000000000000 nopd // FAKE OPERAND GET S0 from PRAM, might be 4 or 5 depending if we're in Y or U,V. ldc s0,4 // index scale factor
000A 000004620002 ldc i3,2 // increment between columns
000B 000005E20002 ldc lpc,2
000C 00001412001E stc i0,#oI0STORE
000D 000000000000 nopd
000E 000014820021 ldc s0,#oS0STORE
000F 000000000000 nopd
dct_vert:
0010 00001402001E ldc i0,#oI0STORE // RETRIEVE i0 //point to data
0011 000000000000 nopd
0012 000005E20008 ldc lpc,8
dct_horiz:
//J Phase starts
0013 000008040000 ld r0,[i0] //J0
0014 000008240004 ld r1,[i0+4] //J1
0015 000008840007 ld r4,[i0+7]
0016 000009822D41 ld r12,S_5
0017 380808E40001 addsub r0,r1,r0; ld r7,[i0+1] //L0; L1
0018 426208440002 mul r4,r12,r4; ld r2,[i0+2] //J4; J2
0019 43E388640006 mul r7,r12,r7; ld r3,[i0+6] //J7; J3
001A 000008A40003 ld r5,[i0+3] //J5
001B 3BA388C40005 addsub r7,r4,r7; ld r6,[i0+5] //K4,K7 ;J6
001C 3BAB892222A2 addsub r7,r5,r7; ld r9,K6c //L5,L7
001D 3A320962AC62 addsub r4,r6,r4; ld r11,nK6s //L6,L4
001E 414F8942539E mul r2,r9,r15; ld r10,K6s
001F 49D900000000 macc r3,r11,r2 //L2
0020 415789224B41 mul r2,r10,r15; ld r9,K3c
0021 49C98962CDB8 macc r3,r9,r3; ld r11,nK3s //L3
///J, K, L phase done
///M Phase starts
0022 424F89423248 mul r4,r9,r15; ld r10,K3s
0023 4BDA00000000 macc r7,r11,r4; //M4
0024 4257892258C5 mul r4,r10,r15; ld r9,K1c
0025 4BCB8962EE58 macc r7,r9,r7; ld r11,nK1s //M7
0026 42CF894211A8 mul r5,r9,r15; ld r10,K1s
0027 4B5A80000000 macc r6,r11,r5 //M5
0028 42D780000000 mul r5,r10,r15
0029 4B4B00000000 macc r6,r9,r6 //M6
002A 000000000000 nopd //addsub can not after macc immediately
002B 389080000000 addsub r1,r2,r1 //M2,M1
002C 381800000000 addsub r0,r3,r0 //M3,M0
////M phase ends
////O phase starts
002D 383800000000 addsub r0,r7,r0
002E 38B08C040000 addsub r1,r6,r1; st r0,[i0+0]
002F 39290CE40007 addsub r2,r5,r2; st r7,[i0+7]
0030 39A18C240001 addsub r3,r4,r3; st r1,[i0+1]
0031 00000CC40006 st r6,[i0+6]
0032 00000C440002 st r2,[i0+2]
0033 00000CA40005 st r5,[i0+5]
0034 00000C640003 st r3,[i0+3]
0035 00000C840004 st r4,[i0+4]
////O phase ends
0036 000000C00013 loop dct_horiz
0037 000001000000 addi0 // executed in delay slot
0038 000004820001 ldc s0,1 // while s0=1, code inside dct_vert process data row by row
0039 000000C00010 loop dct_vert
003A 00001462001F ldc i3,#oI3STORE0 //GET row increment
003B 000000000000 nopd
003C 000000A00000 ret
003D 000000000000 nopd
//wait
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