selec.vhd

来自「文件夹里面有两个文件」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY selec IS
PORT(
     bo_select:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
     CLK:IN STD_LOGIC;
     sin:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     pulse:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     angle:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     bo_xing:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END selec;
ARCHITECTURE xuanze OF selec IS
BEGIN
   P1:PROCESS(CLK)
      BEGIN
      IF(CLK'EVENT AND CLK='1')THEN
          IF(bo_select="00")THEN
              bo_xing<=sin;
          END IF;
          IF(bo_select="01")THEN
              bo_xing<=pulse;
          END IF;
          IF(bo_select="10")THEN
              bo_xing<=angle;
          END IF;
       END IF;
   END PROCESS P1;
END xuanze;