dds.hier_info

文件夹里面有两个文件

|boxing
int0 <= kbscan:inst6.int0
clk => kbscan:inst6.clk_kb
clk => inst7.IN0
clk => selec:inst8.CLK
clk => lpm_rom3:inst4.clock
clk => pin:inst1.CLK
clk => lpm_rom1:inst3.clock
clk => lpm_rom0:inst.clock
row[0] => kbscan:inst6.row[0]
row[1] => kbscan:inst6.row[1]
row[2] => kbscan:inst6.row[2]
row[3] => kbscan:inst6.row[3]
cs4 <= inst7.DB_MAX_OUTPUT_PORT_TYPE
bo_xing[0] <= selec:inst8.bo_xing[0]
bo_xing[1] <= selec:inst8.bo_xing[1]
bo_xing[2] <= selec:inst8.bo_xing[2]
bo_xing[3] <= selec:inst8.bo_xing[3]
bo_xing[4] <= selec:inst8.bo_xing[4]
bo_xing[5] <= selec:inst8.bo_xing[5]
bo_xing[6] <= selec:inst8.bo_xing[6]
bo_xing[7] <= selec:inst8.bo_xing[7]
start => pass:inst2.start
freq[0] => pass:inst2.freq_in[0]
freq[1] => pass:inst2.freq_in[1]
freq[2] => pass:inst2.freq_in[2]
freq[3] => pass:inst2.freq_in[3]
freq[4] => pass:inst2.freq_in[4]
freq[5] => pass:inst2.freq_in[5]
freq[6] => pass:inst2.freq_in[6]
freq[7] => pass:inst2.freq_in[7]
bo_select[0] => selec:inst8.bo_select[0]
bo_select[1] => selec:inst8.bo_select[1]
col[0] <= kbscan:inst6.col[0]
col[1] <= kbscan:inst6.col[1]
col[2] <= kbscan:inst6.col[2]
col[3] <= kbscan:inst6.col[3]
data[0] <= kbscan:inst6.data[0]
data[1] <= kbscan:inst6.data[1]
data[2] <= kbscan:inst6.data[2]
data[3] <= kbscan:inst6.data[3]


|boxing|kbscan:inst6
row[0] => Equal~0.IN7
row[0] => Mux~0.IN19
row[0] => Mux~5.IN19
row[0] => Mux~6.IN19
row[0] => Mux~8.IN19
row[0] => Mux~9.IN19
row[0] => Mux~10.IN19
row[0] => Mux~12.IN19
row[0] => Mux~13.IN19
row[0] => Mux~14.IN19
row[0] => Mux~16.IN19
row[0] => Mux~17.IN19
row[0] => Mux~18.IN19
row[0] => Mux~20.IN19
row[1] => Equal~0.IN6
row[1] => Mux~0.IN18
row[1] => Mux~5.IN18
row[1] => Mux~6.IN18
row[1] => Mux~8.IN18
row[1] => Mux~9.IN18
row[1] => Mux~10.IN18
row[1] => Mux~12.IN18
row[1] => Mux~13.IN18
row[1] => Mux~14.IN18
row[1] => Mux~16.IN18
row[1] => Mux~17.IN18
row[1] => Mux~18.IN18
row[1] => Mux~20.IN18
row[2] => Equal~0.IN5
row[2] => Mux~0.IN17
row[2] => Mux~5.IN17
row[2] => Mux~6.IN17
row[2] => Mux~8.IN17
row[2] => Mux~9.IN17
row[2] => Mux~10.IN17
row[2] => Mux~12.IN17
row[2] => Mux~13.IN17
row[2] => Mux~14.IN17
row[2] => Mux~16.IN17
row[2] => Mux~17.IN17
row[2] => Mux~18.IN17
row[2] => Mux~20.IN17
row[3] => Equal~0.IN4
row[3] => Mux~0.IN16
row[3] => Mux~5.IN16
row[3] => Mux~6.IN16
row[3] => Mux~8.IN16
row[3] => Mux~9.IN16
row[3] => Mux~10.IN16
row[3] => Mux~12.IN16
row[3] => Mux~13.IN16
row[3] => Mux~14.IN16
row[3] => Mux~16.IN16
row[3] => Mux~17.IN16
row[3] => Mux~18.IN16
row[3] => Mux~20.IN16
clk_kb => cnt[0].CLK
clk_kb => cnt[1].CLK
col[0] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
col[1] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
col[2] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
col[3] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= process1~4.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= process1~3.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= process1~2.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= process1~1.DB_MAX_OUTPUT_PORT_TYPE
int0 <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE


|boxing|selec:inst8
bo_select[0] => Equal~0.IN3
bo_select[0] => Equal~1.IN3
bo_select[0] => Equal~2.IN3
bo_select[1] => Equal~0.IN2
bo_select[1] => Equal~1.IN2
bo_select[1] => Equal~2.IN2
CLK => bo_xing[6]~reg0.CLK
CLK => bo_xing[5]~reg0.CLK
CLK => bo_xing[4]~reg0.CLK
CLK => bo_xing[3]~reg0.CLK
CLK => bo_xing[2]~reg0.CLK
CLK => bo_xing[1]~reg0.CLK
CLK => bo_xing[0]~reg0.CLK
CLK => bo_xing[7]~reg0.CLK
sin[0] => bo_xing~7.DATAB
sin[1] => bo_xing~6.DATAB
sin[2] => bo_xing~5.DATAB
sin[3] => bo_xing~4.DATAB
sin[4] => bo_xing~3.DATAB
sin[5] => bo_xing~2.DATAB
sin[6] => bo_xing~1.DATAB
sin[7] => bo_xing~0.DATAB
pulse[0] => bo_xing~15.DATAB
pulse[1] => bo_xing~14.DATAB
pulse[2] => bo_xing~13.DATAB
pulse[3] => bo_xing~12.DATAB
pulse[4] => bo_xing~11.DATAB
pulse[5] => bo_xing~10.DATAB
pulse[6] => bo_xing~9.DATAB
pulse[7] => bo_xing~8.DATAB
angle[0] => bo_xing~23.DATAB
angle[1] => bo_xing~22.DATAB
angle[2] => bo_xing~21.DATAB
angle[3] => bo_xing~20.DATAB
angle[4] => bo_xing~19.DATAB
angle[5] => bo_xing~18.DATAB
angle[6] => bo_xing~17.DATAB
angle[7] => bo_xing~16.DATAB
bo_xing[0] <= bo_xing[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bo_xing[1] <= bo_xing[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bo_xing[2] <= bo_xing[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bo_xing[3] <= bo_xing[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bo_xing[4] <= bo_xing[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bo_xing[5] <= bo_xing[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bo_xing[6] <= bo_xing[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bo_xing[7] <= bo_xing[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|boxing|lpm_rom3:inst4
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|boxing|lpm_rom3:inst4|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altrom:rom.address[0]
address_a[1] => altrom:rom.address[1]
address_a[2] => altrom:rom.address[2]
address_a[3] => altrom:rom.address[3]
address_a[4] => altrom:rom.address[4]
address_a[5] => altrom:rom.address[5]
address_a[6] => altrom:rom.address[6]
address_a[7] => altrom:rom.address[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altrom:rom.clocki
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altrom:rom.q[0]
q_a[1] <= altrom:rom.q[1]
q_a[2] <= altrom:rom.q[2]
q_a[3] <= altrom:rom.q[3]
q_a[4] <= altrom:rom.q[4]
q_a[5] <= altrom:rom.q[5]
q_a[6] <= altrom:rom.q[6]
q_a[7] <= altrom:rom.q[7]
q_b[0] <= <GND>


|boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
clocki => segment[0][7].CLK0
clocki => segment[0][6].CLK0
clocki => segment[0][5].CLK0
clocki => segment[0][4].CLK0
clocki => segment[0][3].CLK0
clocki => segment[0][2].CLK0
clocki => segment[0][1].CLK0
clocki => segment[0][0].CLK0
clocko => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT


|boxing|pin:inst1
CLK => address[6]~reg0.CLK
CLK => address[5]~reg0.CLK
CLK => address[4]~reg0.CLK
CLK => address[3]~reg0.CLK
CLK => address[2]~reg0.CLK
CLK => address[1]~reg0.CLK
CLK => address[0]~reg0.CLK
CLK => address_reg[7].CLK
CLK => address_reg[6].CLK
CLK => address_reg[5].CLK
CLK => address_reg[4].CLK
CLK => address_reg[3].CLK
CLK => address_reg[2].CLK
CLK => address_reg[1].CLK
CLK => address_reg[0].CLK
CLK => address[7]~reg0.CLK
freq[0] => add~0.IN8
freq[1] => add~0.IN7
freq[2] => add~0.IN6
freq[3] => add~0.IN5
freq[4] => add~0.IN4
freq[5] => add~0.IN3
freq[6] => add~0.IN2
freq[7] => add~0.IN1
address[0] <= address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[1] <= address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[2] <= address[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[3] <= address[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[4] <= address[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[5] <= address[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[6] <= address[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address[7] <= address[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|boxing|pass:inst2
start => freq_out[6]~reg0.CLK
start => freq_out[5]~reg0.CLK
start => freq_out[4]~reg0.CLK
start => freq_out[3]~reg0.CLK
start => freq_out[2]~reg0.CLK
start => freq_out[1]~reg0.CLK
start => freq_out[0]~reg0.CLK
start => freq_out[7]~reg0.CLK
freq_in[0] => freq_out[0]~reg0.DATAIN
freq_in[1] => freq_out[1]~reg0.DATAIN
freq_in[2] => freq_out[2]~reg0.DATAIN
freq_in[3] => freq_out[3]~reg0.DATAIN
freq_in[4] => freq_out[4]~reg0.DATAIN
freq_in[5] => freq_out[5]~reg0.DATAIN
freq_in[6] => freq_out[6]~reg0.DATAIN
freq_in[7] => freq_out[7]~reg0.DATAIN
freq_out[0] <= freq_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq_out[1] <= freq_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq_out[2] <= freq_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq_out[3] <= freq_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE