dds.map.qmsg

文件夹里面有两个文件

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/altrom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altrom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altrom " "Info: Found entity 1: altrom" {  } { { "altrom.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altrom.tdf" 75 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom " "Info: Elaborating entity \"altrom\" for hierarchy \"lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom\"" {  } { { "altsyncram.tdf" "rom" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 853 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin pin:inst1 " "Info: Elaborating entity \"pin\" for hierarchy \"pin:inst1\"" {  } { { "boxing.bdf" "inst1" { Schematic "F:/dds/boxing.bdf" { { -32 -32 136 64 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pass pass:inst2 " "Info: Elaborating entity \"pass\" for hierarchy \"pass:inst2\"" {  } { { "boxing.bdf" "inst2" { Schematic "F:/dds/boxing.bdf" { { -32 -256 -72 64 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom1.vhd 2 1 " "Warning: Using design file lpm_rom1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom1-SYN " "Info: Found design unit 1: lpm_rom1-SYN" {  } { { "lpm_rom1.vhd" "" { Text "F:/dds/lpm_rom1.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom1 " "Info: Found entity 1: lpm_rom1" {  } { { "lpm_rom1.vhd" "" { Text "F:/dds/lpm_rom1.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom1 lpm_rom1:inst3 " "Info: Elaborating entity \"lpm_rom1\" for hierarchy \"lpm_rom1:inst3\"" {  } { { "boxing.bdf" "inst3" { Schematic "F:/dds/boxing.bdf" { { 176 256 416 256 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom1:inst3\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom1:inst3\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom1.vhd" "altsyncram_component" { Text "F:/dds/lpm_rom1.vhd" 80 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom1:inst3\|altsyncram:altsyncram_component\|altrom:rom " "Info: Elaborating entity \"altrom\" for hierarchy \"lpm_rom1:inst3\|altsyncram:altsyncram_component\|altrom:rom\"" {  } { { "altsyncram.tdf" "rom" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 853 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom0.vhd 2 1 " "Warning: Using design file lpm_rom0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom0-SYN " "Info: Found design unit 1: lpm_rom0-SYN" {  } { { "lpm_rom0.vhd" "" { Text "F:/dds/lpm_rom0.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Info: Found entity 1: lpm_rom0" {  } { { "lpm_rom0.vhd" "" { Text "F:/dds/lpm_rom0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0 lpm_rom0:inst " "Info: Elaborating entity \"lpm_rom0\" for hierarchy \"lpm_rom0:inst\"" {  } { { "boxing.bdf" "inst" { Schematic "F:/dds/boxing.bdf" { { 72 256 416 152 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.vhd" "altsyncram_component" { Text "F:/dds/lpm_rom0.vhd" 80 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom0:inst\|altsyncram:altsyncram_component\|altrom:rom " "Info: Elaborating entity \"altrom\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altrom:rom\"" {  } { { "altsyncram.tdf" "rom" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 853 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "pin:inst1\|address_reg\[0\] pin:inst1\|address\[0\] " "Info: Duplicate register \"pin:inst1\|address_reg\[0\]\" merged to single register \"pin:inst1\|address\[0\]\"" {  } { { "pin.vhd" "" { Text "F:/dds/pin.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pin:inst1\|address_reg\[1\] pin:inst1\|address\[1\] " "Info: Duplicate register \"pin:inst1\|address_reg\[1\]\" merged to single register \"pin:inst1\|address\[1\]\"" {  } { { "pin.vhd" "" { Text "F:/dds/pin.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pin:inst1\|address_reg\[2\] pin:inst1\|address\[2\] " "Info: Duplicate register \"pin:inst1\|address_reg\[2\]\" merged to single register \"pin:inst1\|address\[2\]\"" {  } { { "pin.vhd" "" { Text "F:/dds/pin.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pin:inst1\|address_reg\[3\] pin:inst1\|address\[3\] " "Info: Duplicate register \"pin:inst1\|address_reg\[3\]\" merged to single register \"pin:inst1\|address\[3\]\"" {  } { { "pin.vhd" "" { Text "F:/dds/pin.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pin:inst1\|address_reg\[4\] pin:inst1\|address\[4\] " "Info: Duplicate register \"pin:inst1\|address_reg\[4\]\" merged to single register \"pin:inst1\|address\[4\]\"" {  } { { "pin.vhd" "" { Text "F:/dds/pin.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pin:inst1\|address_reg\[5\] pin:inst1\|address\[5\] " "Info: Duplicate register \"pin:inst1\|address_reg\[5\]\" merged to single register \"pin:inst1\|address\[5\]\"" {  } { { "pin.vhd" "" { Text "F:/dds/pin.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pin:inst1\|address_reg\[6\] pin:inst1\|address\[6\] " "Info: Duplicate register \"pin:inst1\|address_reg\[6\]\" merged to single register \"pin:inst1\|address\[6\]\"" {  } { { "pin.vhd" "" { Text "F:/dds/pin.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pin:inst1\|address_reg\[7\] pin:inst1\|address\[7\] " "Info: Duplicate register \"pin:inst1\|address_reg\[7\]\" merged to single register \"pin:inst1\|address\[7\]\"" {  } { { "pin.vhd" "" { Text "F:/dds/pin.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "115 " "Info: Implemented 115 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "16 " "Info: Implemented 16 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "57 " "Info: Implemented 57 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "24 " "Info: Implemented 24 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 09 08:02:53 2008 " "Info: Processing ended: Wed Jan 09 08:02:53 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}