dds.tan.qmsg

文件夹里面有两个文件

{ "Info" "ITDB_FULL_TPD_RESULT" "row\[0\] data\[1\] 19.100 ns Longest " "Info: Longest tpd from source pin \"row\[0\]\" to destination pin \"data\[1\]\" is 19.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns row\[0\] 1 PIN PIN_62 8 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_62; Fanout = 8; PIN Node = 'row\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { row[0] } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -120 64 232 -104 "row\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.300 ns) 8.800 ns kbscan:inst6\|int0~3 2 COMB LC1_C12 5 " "Info: 2: + IC(3.000 ns) + CELL(2.300 ns) = 8.800 ns; Loc. = LC1_C12; Fanout = 5; COMB Node = 'kbscan:inst6\|int0~3'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "5.300 ns" { row[0] kbscan:inst6|int0~3 } "NODE_NAME" } "" } } { "kbscan.vhd" "" { Text "F:/dds/kbscan.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.200 ns) + CELL(6.100 ns) 19.100 ns data\[1\] 3 PIN PIN_11 0 " "Info: 3: + IC(4.200 ns) + CELL(6.100 ns) = 19.100 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'data\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "10.300 ns" { kbscan:inst6|int0~3 data[1] } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -104 448 624 -88 "data\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.900 ns ( 62.30 % ) " "Info: Total cell delay = 11.900 ns ( 62.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns ( 37.70 % ) " "Info: Total interconnect delay = 7.200 ns ( 37.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "19.100 ns" { row[0] kbscan:inst6|int0~3 data[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "19.100 ns" { row[0] row[0]~out kbscan:inst6|int0~3 data[1] } { 0.000ns 0.000ns 3.000ns 4.200ns } { 0.000ns 3.500ns 2.300ns 6.100ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "selec:inst8\|bo_xing\[4\] bo_select\[1\] clk 3.800 ns register " "Info: th for register \"selec:inst8\|bo_xing\[4\]\" (data pin = \"bo_select\[1\]\", clock pin = \"clk\") is 3.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.700 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk 1 CLK PIN_19 211 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 211; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { clk } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -104 -240 -72 -88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.200 ns) + CELL(0.000 ns) 11.700 ns selec:inst8\|bo_xing\[4\] 2 REG LC3_C17 2 " "Info: 2: + IC(8.200 ns) + CELL(0.000 ns) = 11.700 ns; Loc. = LC3_C17; Fanout = 2; REG Node = 'selec:inst8\|bo_xing\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "8.200 ns" { clk selec:inst8|bo_xing[4] } "NODE_NAME" } "" } } { "selec.vhd" "" { Text "F:/dds/selec.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 29.91 % ) " "Info: Total cell delay = 3.500 ns ( 29.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.200 ns ( 70.09 % ) " "Info: Total interconnect delay = 8.200 ns ( 70.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "11.700 ns" { clk selec:inst8|bo_xing[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.700 ns" { clk clk~out selec:inst8|bo_xing[4] } { 0.000ns 0.000ns 8.200ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "selec.vhd" "" { Text "F:/dds/selec.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns bo_select\[1\] 1 PIN PIN_7 12 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_7; Fanout = 12; PIN Node = 'bo_select\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { bo_select[1] } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -8 272 440 8 "bo_select\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.700 ns) 9.500 ns selec:inst8\|bo_xing\[4\] 2 REG LC3_C17 2 " "Info: 2: + IC(4.300 ns) + CELL(1.700 ns) = 9.500 ns; Loc. = LC3_C17; Fanout = 2; REG Node = 'selec:inst8\|bo_xing\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "6.000 ns" { bo_select[1] selec:inst8|bo_xing[4] } "NODE_NAME" } "" } } { "selec.vhd" "" { Text "F:/dds/selec.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 54.74 % ) " "Info: Total cell delay = 5.200 ns ( 54.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 45.26 % ) " "Info: Total interconnect delay = 4.300 ns ( 45.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "9.500 ns" { bo_select[1] selec:inst8|bo_xing[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.500 ns" { bo_select[1] bo_select[1]~out selec:inst8|bo_xing[4] } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.500ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "11.700 ns" { clk selec:inst8|bo_xing[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.700 ns" { clk clk~out selec:inst8|bo_xing[4] } { 0.000ns 0.000ns 8.200ns } { 0.000ns 3.500ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "9.500 ns" { bo_select[1] selec:inst8|bo_xing[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.500 ns" { bo_select[1] bo_select[1]~out selec:inst8|bo_xing[4] } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.500ns 1.700ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 09 08:03:07 2008 " "Info: Processing ended: Wed Jan 09 08:03:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}