dds.tan.qmsg

文件夹里面有两个文件

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 56 " "Warning: Circuit may not operate. Detected 56 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "pin:inst1\|address\[1\] lpm_rom0:inst\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra1 clk 3.5 ns " "Info: Found hold time violation between source  pin or register \"pin:inst1\|address\[1\]\" and destination pin or register \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra1\" for clock \"clk\" (Hold time is 3.5 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.000 ns + Largest " "Info: + Largest clock skew is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.200 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to destination memory is 12.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk 1 CLK PIN_19 211 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 211; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { clk } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -104 -240 -72 -88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.700 ns) + CELL(0.000 ns) 12.200 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra1 2 MEM EC4_C 1 " "Info: 2: + IC(8.700 ns) + CELL(0.000 ns) = 12.200 ns; Loc. = EC4_C; Fanout = 1; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "8.700 ns" { clk lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 28.69 % ) " "Info: Total cell delay = 3.500 ns ( 28.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.700 ns ( 71.31 % ) " "Info: Total interconnect delay = 8.700 ns ( 71.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "12.200 ns" { clk lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.200 ns" { clk clk~out lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } { 0.000ns 0.000ns 8.700ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.200 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk 1 CLK PIN_19 211 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 211; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { clk } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -104 -240 -72 -88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.000 ns) 6.200 ns pin:inst1\|address\[1\] 2 REG LC1_A2 26 " "Info: 2: + IC(2.700 ns) + CELL(0.000 ns) = 6.200 ns; Loc. = LC1_A2; Fanout = 26; REG Node = 'pin:inst1\|address\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "2.700 ns" { clk pin:inst1|address[1] } "NODE_NAME" } "" } } { "pin.vhd" "" { Text "F:/dds/pin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 56.45 % ) " "Info: Total cell delay = 3.500 ns ( 56.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 43.55 % ) " "Info: Total interconnect delay = 2.700 ns ( 43.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "6.200 ns" { clk pin:inst1|address[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.200 ns" { clk clk~out pin:inst1|address[1] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "12.200 ns" { clk lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.200 ns" { clk clk~out lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } { 0.000ns 0.000ns 8.700ns } { 0.000ns 3.500ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "6.200 ns" { clk pin:inst1|address[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.200 ns" { clk clk~out pin:inst1|address[1] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "pin.vhd" "" { Text "F:/dds/pin.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns - Shortest register memory " "Info: - Shortest register to memory delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pin:inst1\|address\[1\] 1 REG LC1_A2 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A2; Fanout = 26; REG Node = 'pin:inst1\|address\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { pin:inst1|address[1] } "NODE_NAME" } "" } } { "pin.vhd" "" { Text "F:/dds/pin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.000 ns) 3.900 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra1 2 MEM EC4_C 1 " "Info: 2: + IC(3.900 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = EC4_C; Fanout = 1; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "3.900 ns" { pin:inst1|address[1] lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns ( 100.00 % ) " "Info: Total interconnect delay = 3.900 ns ( 100.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "3.900 ns" { pin:inst1|address[1] lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { pin:inst1|address[1] lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } { 0.000ns 3.900ns } { 0.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "2.500 ns + " "Info: + Micro hold delay of destination is 2.500 ns" {  } { { "altrom.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "12.200 ns" { clk lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.200 ns" { clk clk~out lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } { 0.000ns 0.000ns 8.700ns } { 0.000ns 3.500ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "6.200 ns" { clk pin:inst1|address[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.200 ns" { clk clk~out pin:inst1|address[1] } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.500ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "3.900 ns" { pin:inst1|address[1] lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { pin:inst1|address[1] lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra1 } { 0.000ns 3.900ns } { 0.000ns 0.000ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "selec:inst8\|bo_xing\[7\] bo_select\[1\] clk 6.700 ns register " "Info: tsu for register \"selec:inst8\|bo_xing\[7\]\" (data pin = \"bo_select\[1\]\", clock pin = \"clk\") is 6.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.800 ns + Longest pin register " "Info: + Longest pin to register delay is 11.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns bo_select\[1\] 1 PIN PIN_7 12 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_7; Fanout = 12; PIN Node = 'bo_select\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { bo_select[1] } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -8 272 440 8 "bo_select\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(2.300 ns) 9.500 ns selec:inst8\|bo_xing~56 2 COMB LC1_A15 1 " "Info: 2: + IC(3.700 ns) + CELL(2.300 ns) = 9.500 ns; Loc. = LC1_A15; Fanout = 1; COMB Node = 'selec:inst8\|bo_xing~56'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "6.000 ns" { bo_select[1] selec:inst8|bo_xing~56 } "NODE_NAME" } "" } } { "selec.vhd" "" { Text "F:/dds/selec.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 11.800 ns selec:inst8\|bo_xing\[7\] 3 REG LC8_A15 2 " "Info: 3: + IC(0.600 ns) + CELL(1.700 ns) = 11.800 ns; Loc. = LC8_A15; Fanout = 2; REG Node = 'selec:inst8\|bo_xing\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "2.300 ns" { selec:inst8|bo_xing~56 selec:inst8|bo_xing[7] } "NODE_NAME" } "" } } { "selec.vhd" "" { Text "F:/dds/selec.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns ( 63.56 % ) " "Info: Total cell delay = 7.500 ns ( 63.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 36.44 % ) " "Info: Total interconnect delay = 4.300 ns ( 36.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "11.800 ns" { bo_select[1] selec:inst8|bo_xing~56 selec:inst8|bo_xing[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.800 ns" { bo_select[1] bo_select[1]~out selec:inst8|bo_xing~56 selec:inst8|bo_xing[7] } { 0.000ns 0.000ns 3.700ns 0.600ns } { 0.000ns 3.500ns 2.300ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "selec.vhd" "" { Text "F:/dds/selec.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.600 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk 1 CLK PIN_19 211 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 211; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { clk } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -104 -240 -72 -88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(0.000 ns) 7.600 ns selec:inst8\|bo_xing\[7\] 2 REG LC8_A15 2 " "Info: 2: + IC(4.100 ns) + CELL(0.000 ns) = 7.600 ns; Loc. = LC8_A15; Fanout = 2; REG Node = 'selec:inst8\|bo_xing\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "4.100 ns" { clk selec:inst8|bo_xing[7] } "NODE_NAME" } "" } } { "selec.vhd" "" { Text "F:/dds/selec.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 46.05 % ) " "Info: Total cell delay = 3.500 ns ( 46.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.100 ns ( 53.95 % ) " "Info: Total interconnect delay = 4.100 ns ( 53.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "7.600 ns" { clk selec:inst8|bo_xing[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { clk clk~out selec:inst8|bo_xing[7] } { 0.000ns 0.000ns 4.100ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "11.800 ns" { bo_select[1] selec:inst8|bo_xing~56 selec:inst8|bo_xing[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.800 ns" { bo_select[1] bo_select[1]~out selec:inst8|bo_xing~56 selec:inst8|bo_xing[7] } { 0.000ns 0.000ns 3.700ns 0.600ns } { 0.000ns 3.500ns 2.300ns 1.700ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "7.600 ns" { clk selec:inst8|bo_xing[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { clk clk~out selec:inst8|bo_xing[7] } { 0.000ns 0.000ns 4.100ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[3\] kbscan:inst6\|cnt\[0\] 29.700 ns register " "Info: tco from clock \"clk\" to destination pin \"data\[3\]\" through register \"kbscan:inst6\|cnt\[0\]\" is 29.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk 1 CLK PIN_19 211 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 211; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { clk } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -104 -240 -72 -88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(9.100 ns) + CELL(0.000 ns) 12.600 ns kbscan:inst6\|cnt\[0\] 2 REG LC6_C7 12 " "Info: 2: + IC(9.100 ns) + CELL(0.000 ns) = 12.600 ns; Loc. = LC6_C7; Fanout = 12; REG Node = 'kbscan:inst6\|cnt\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "9.100 ns" { clk kbscan:inst6|cnt[0] } "NODE_NAME" } "" } } { "kbscan.vhd" "" { Text "F:/dds/kbscan.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 27.78 % ) " "Info: Total cell delay = 3.500 ns ( 27.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.100 ns ( 72.22 % ) " "Info: Total interconnect delay = 9.100 ns ( 72.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "12.600 ns" { clk kbscan:inst6|cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.600 ns" { clk clk~out kbscan:inst6|cnt[0] } { 0.000ns 0.000ns 9.100ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "kbscan.vhd" "" { Text "F:/dds/kbscan.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.000 ns + Longest register pin " "Info: + Longest register to pin delay is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns kbscan:inst6\|cnt\[0\] 1 REG LC6_C7 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_C7; Fanout = 12; REG Node = 'kbscan:inst6\|cnt\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { kbscan:inst6|cnt[0] } "NODE_NAME" } "" } } { "kbscan.vhd" "" { Text "F:/dds/kbscan.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns kbscan:inst6\|add~14 2 COMB LC2_C7 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC2_C7; Fanout = 1; COMB Node = 'kbscan:inst6\|add~14'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "2.900 ns" { kbscan:inst6|cnt[0] kbscan:inst6|add~14 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 6.900 ns kbscan:inst6\|Mux~664 3 COMB LC5_C2 1 " "Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 6.900 ns; Loc. = LC5_C2; Fanout = 1; COMB Node = 'kbscan:inst6\|Mux~664'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "4.000 ns" { kbscan:inst6|add~14 kbscan:inst6|Mux~664 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 9.800 ns kbscan:inst6\|Mux~665 4 COMB LC2_C2 1 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 9.800 ns; Loc. = LC2_C2; Fanout = 1; COMB Node = 'kbscan:inst6\|Mux~665'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "2.900 ns" { kbscan:inst6|Mux~664 kbscan:inst6|Mux~665 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(5.100 ns) 16.000 ns data\[3\] 5 PIN PIN_9 0 " "Info: 5: + IC(1.100 ns) + CELL(5.100 ns) = 16.000 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'data\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "6.200 ns" { kbscan:inst6|Mux~665 data[3] } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -104 448 624 -88 "data\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.500 ns ( 71.88 % ) " "Info: Total cell delay = 11.500 ns ( 71.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns ( 28.13 % ) " "Info: Total interconnect delay = 4.500 ns ( 28.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "16.000 ns" { kbscan:inst6|cnt[0] kbscan:inst6|add~14 kbscan:inst6|Mux~664 kbscan:inst6|Mux~665 data[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "16.000 ns" { kbscan:inst6|cnt[0] kbscan:inst6|add~14 kbscan:inst6|Mux~664 kbscan:inst6|Mux~665 data[3] } { 0.000ns 0.600ns 2.200ns 0.600ns 1.100ns } { 0.000ns 2.300ns 1.800ns 2.300ns 5.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "12.600 ns" { clk kbscan:inst6|cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.600 ns" { clk clk~out kbscan:inst6|cnt[0] } { 0.000ns 0.000ns 9.100ns } { 0.000ns 3.500ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "16.000 ns" { kbscan:inst6|cnt[0] kbscan:inst6|add~14 kbscan:inst6|Mux~664 kbscan:inst6|Mux~665 data[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "16.000 ns" { kbscan:inst6|cnt[0] kbscan:inst6|add~14 kbscan:inst6|Mux~664 kbscan:inst6|Mux~665 data[3] } { 0.000ns 0.600ns 2.200ns 0.600ns 1.100ns } { 0.000ns 2.300ns 1.800ns 2.300ns 5.100ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}