dds.tan.qmsg

文件夹里面有两个文件

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -104 -240 -72 -88 "clk" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "start " "Info: Assuming node \"start\" is an undefined clock" {  } { { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -8 -448 -280 8 "start" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "start" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra0 register selec:inst8\|bo_xing\[1\] 41.15 MHz 24.3 ns Internal " "Info: Clock \"clk\" has Internal fmax of 41.15 MHz between source memory \"lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra0\" and destination register \"selec:inst8\|bo_xing\[1\]\" (period= 24.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.400 ns + Longest memory register " "Info: + Longest memory to register delay is 20.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra0 1 MEM EC1_C 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC1_C; Fanout = 1; MEM Node = 'lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.700 ns) 10.700 ns lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~mem_cell_ra0 2 MEM EC1_C 1 " "Info: 2: + IC(0.000 ns) + CELL(10.700 ns) = 10.700 ns; Loc. = EC1_C; Fanout = 1; MEM Node = 'lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~mem_cell_ra0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "10.700 ns" { lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~mem_cell_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 13.200 ns lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\] 3 MEM EC1_C 1 " "Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 13.200 ns; Loc. = EC1_C; Fanout = 1; MEM Node = 'lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "2.500 ns" { lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~mem_cell_ra0 lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1] } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.300 ns) 18.100 ns selec:inst8\|bo_xing~68 4 COMB LC2_C21 1 " "Info: 4: + IC(2.600 ns) + CELL(2.300 ns) = 18.100 ns; Loc. = LC2_C21; Fanout = 1; COMB Node = 'selec:inst8\|bo_xing~68'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "4.900 ns" { lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1] selec:inst8|bo_xing~68 } "NODE_NAME" } "" } } { "selec.vhd" "" { Text "F:/dds/selec.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 20.400 ns selec:inst8\|bo_xing\[1\] 5 REG LC8_C21 2 " "Info: 5: + IC(0.600 ns) + CELL(1.700 ns) = 20.400 ns; Loc. = LC8_C21; Fanout = 2; REG Node = 'selec:inst8\|bo_xing\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "2.300 ns" { selec:inst8|bo_xing~68 selec:inst8|bo_xing[1] } "NODE_NAME" } "" } } { "selec.vhd" "" { Text "F:/dds/selec.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.200 ns ( 84.31 % ) " "Info: Total cell delay = 17.200 ns ( 84.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns ( 15.69 % ) " "Info: Total interconnect delay = 3.200 ns ( 15.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "20.400 ns" { lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~mem_cell_ra0 lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1] selec:inst8|bo_xing~68 selec:inst8|bo_xing[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.400 ns" { lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~mem_cell_ra0 lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1] selec:inst8|bo_xing~68 selec:inst8|bo_xing[1] } { 0.000ns 0.000ns 0.000ns 2.600ns 0.600ns } { 0.000ns 10.700ns 2.500ns 2.300ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.800 ns - Smallest " "Info: - Smallest clock skew is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 11.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk 1 CLK PIN_19 211 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 211; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { clk } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -104 -240 -72 -88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.900 ns) + CELL(0.000 ns) 11.400 ns selec:inst8\|bo_xing\[1\] 2 REG LC8_C21 2 " "Info: 2: + IC(7.900 ns) + CELL(0.000 ns) = 11.400 ns; Loc. = LC8_C21; Fanout = 2; REG Node = 'selec:inst8\|bo_xing\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "7.900 ns" { clk selec:inst8|bo_xing[1] } "NODE_NAME" } "" } } { "selec.vhd" "" { Text "F:/dds/selec.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 30.70 % ) " "Info: Total cell delay = 3.500 ns ( 30.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.900 ns ( 69.30 % ) " "Info: Total interconnect delay = 7.900 ns ( 69.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "11.400 ns" { clk selec:inst8|bo_xing[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.400 ns" { clk clk~out selec:inst8|bo_xing[1] } { 0.000ns 0.000ns 7.900ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.200 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 12.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns clk 1 CLK PIN_19 211 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_19; Fanout = 211; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "" { clk } "NODE_NAME" } "" } } { "boxing.bdf" "" { Schematic "F:/dds/boxing.bdf" { { -104 -240 -72 -88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.700 ns) + CELL(0.000 ns) 12.200 ns lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra0 2 MEM EC1_C 1 " "Info: 2: + IC(8.700 ns) + CELL(0.000 ns) = 12.200 ns; Loc. = EC1_C; Fanout = 1; MEM Node = 'lpm_rom3:inst4\|altsyncram:altsyncram_component\|altrom:rom\|q\[1\]~reg_ra0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "8.700 ns" { clk lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 28.69 % ) " "Info: Total cell delay = 3.500 ns ( 28.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.700 ns ( 71.31 % ) " "Info: Total interconnect delay = 8.700 ns ( 71.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "12.200 ns" { clk lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.200 ns" { clk clk~out lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 } { 0.000ns 0.000ns 8.700ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "11.400 ns" { clk selec:inst8|bo_xing[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.400 ns" { clk clk~out selec:inst8|bo_xing[1] } { 0.000ns 0.000ns 7.900ns } { 0.000ns 3.500ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "12.200 ns" { clk lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.200 ns" { clk clk~out lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 } { 0.000ns 0.000ns 8.700ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "altrom.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "selec.vhd" "" { Text "F:/dds/selec.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "20.400 ns" { lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~mem_cell_ra0 lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1] selec:inst8|bo_xing~68 selec:inst8|bo_xing[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "20.400 ns" { lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~mem_cell_ra0 lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1] selec:inst8|bo_xing~68 selec:inst8|bo_xing[1] } { 0.000ns 0.000ns 0.000ns 2.600ns 0.600ns } { 0.000ns 10.700ns 2.500ns 2.300ns 1.700ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "11.400 ns" { clk selec:inst8|bo_xing[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.400 ns" { clk clk~out selec:inst8|bo_xing[1] } { 0.000ns 0.000ns 7.900ns } { 0.000ns 3.500ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds" "UNKNOWN" "V1" "F:/dds/db/dds.quartus_db" { Floorplan "F:/dds/" "" "12.200 ns" { clk lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.200 ns" { clk clk~out lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1]~reg_ra0 } { 0.000ns 0.000ns 8.700ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "start " "Info: No valid register-to-register data paths exist for clock \"start\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}