pin.vhd

来自「文件夹里面有两个文件」· VHDL 代码 · 共 20 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pin IS
PORT(
     CLK:IN STD_LOGIC;
     freq:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     address:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END pin;
ARCHITECTURE pinlv OF pin IS
SIGNAL address_reg:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
   P1:PROCESS(CLK)
      BEGIN
      IF(CLK'EVENT AND CLK='1')THEN
          address<=address_reg+freq;
          address_reg<=address_reg+freq;
          END IF;          
   END PROCESS P1;
END pinlv;