dds.map.eqn

文件夹里面有两个文件

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--G1L16 is kbscan:inst6|int0~3
--operation mode is normal

G1L16 = row[0] & (row[1] & (row[2] $ row[3]) # !row[1] & row[2] & row[3]) # !row[0] & row[1] & row[2] & row[3];

--G1L17 is kbscan:inst6|int0~4
--operation mode is normal

G1L17 = row[0] & (row[1] & (row[2] $ row[3]) # !row[1] & row[2] & row[3]) # !row[0] & row[1] & row[2] & row[3];


--H1_bo_xing[7] is selec:inst8|bo_xing[7]
--operation mode is normal

H1_bo_xing[7]_lut_out = bo_select[0] & (H1L18 & (H1_bo_xing[7]) # !H1L18 & K2_q[7]) # !bo_select[0] & (H1L18);
H1_bo_xing[7] = DFFEA(H1_bo_xing[7]_lut_out, clk, , , , , );

--H1L17Q is selec:inst8|bo_xing[7]~72
--operation mode is normal

H1L17Q = H1_bo_xing[7];


--H1_bo_xing[6] is selec:inst8|bo_xing[6]
--operation mode is normal

H1_bo_xing[6]_lut_out = bo_select[1] & (H1L19 & (H1_bo_xing[6]) # !H1L19 & K1_q[6]) # !bo_select[1] & (H1L19);
H1_bo_xing[6] = DFFEA(H1_bo_xing[6]_lut_out, clk, , , , , );

--H1L15Q is selec:inst8|bo_xing[6]~73
--operation mode is normal

H1L15Q = H1_bo_xing[6];


--H1_bo_xing[5] is selec:inst8|bo_xing[5]
--operation mode is normal

H1_bo_xing[5]_lut_out = bo_select[0] & (H1L20 & (H1_bo_xing[5]) # !H1L20 & K2_q[5]) # !bo_select[0] & (H1L20);
H1_bo_xing[5] = DFFEA(H1_bo_xing[5]_lut_out, clk, , , , , );

--H1L13Q is selec:inst8|bo_xing[5]~74
--operation mode is normal

H1L13Q = H1_bo_xing[5];


--H1_bo_xing[4] is selec:inst8|bo_xing[4]
--operation mode is normal

H1_bo_xing[4]_lut_out = bo_select[1] & (H1L21 & (H1_bo_xing[4]) # !H1L21 & K1_q[4]) # !bo_select[1] & (H1L21);
H1_bo_xing[4] = DFFEA(H1_bo_xing[4]_lut_out, clk, , , , , );

--H1L11Q is selec:inst8|bo_xing[4]~75
--operation mode is normal

H1L11Q = H1_bo_xing[4];


--H1_bo_xing[3] is selec:inst8|bo_xing[3]
--operation mode is normal

H1_bo_xing[3]_lut_out = bo_select[0] & (H1L22 & (H1_bo_xing[3]) # !H1L22 & K2_q[3]) # !bo_select[0] & (H1L22);
H1_bo_xing[3] = DFFEA(H1_bo_xing[3]_lut_out, clk, , , , , );

--H1L9Q is selec:inst8|bo_xing[3]~76
--operation mode is normal

H1L9Q = H1_bo_xing[3];


--H1_bo_xing[2] is selec:inst8|bo_xing[2]
--operation mode is normal

H1_bo_xing[2]_lut_out = bo_select[1] & (H1L23 & (H1_bo_xing[2]) # !H1L23 & K1_q[2]) # !bo_select[1] & (H1L23);
H1_bo_xing[2] = DFFEA(H1_bo_xing[2]_lut_out, clk, , , , , );

--H1L7Q is selec:inst8|bo_xing[2]~77
--operation mode is normal

H1L7Q = H1_bo_xing[2];


--H1_bo_xing[1] is selec:inst8|bo_xing[1]
--operation mode is normal

H1_bo_xing[1]_lut_out = bo_select[0] & (H1L24 & (H1_bo_xing[1]) # !H1L24 & K2_q[1]) # !bo_select[0] & (H1L24);
H1_bo_xing[1] = DFFEA(H1_bo_xing[1]_lut_out, clk, , , , , );

--H1L5Q is selec:inst8|bo_xing[1]~78
--operation mode is normal

H1L5Q = H1_bo_xing[1];


--H1_bo_xing[0] is selec:inst8|bo_xing[0]
--operation mode is normal

H1_bo_xing[0]_lut_out = bo_select[1] & (H1L25 & (H1_bo_xing[0]) # !H1L25 & K1_q[0]) # !bo_select[1] & (H1L25);
H1_bo_xing[0] = DFFEA(H1_bo_xing[0]_lut_out, clk, , , , , );

--H1L3Q is selec:inst8|bo_xing[0]~79
--operation mode is normal

H1L3Q = H1_bo_xing[0];


--G1_cnt[0] is kbscan:inst6|cnt[0]
--operation mode is normal

G1_cnt[0]_lut_out = !G1_cnt[0];
G1_cnt[0] = DFFEA(G1_cnt[0]_lut_out, clk, , , A1L40, , );

--G1L5Q is kbscan:inst6|cnt[0]~57
--operation mode is normal

G1L5Q = G1_cnt[0];


--G1_cnt[1] is kbscan:inst6|cnt[1]
--operation mode is normal

G1_cnt[1]_lut_out = G1_cnt[0] $ G1_cnt[1];
G1_cnt[1] = DFFEA(G1_cnt[1]_lut_out, clk, , , A1L40, , );

--G1L7Q is kbscan:inst6|cnt[1]~58
--operation mode is normal

G1L7Q = G1_cnt[1];


--G1L8 is kbscan:inst6|col[0]~31
--operation mode is normal

G1L8 = !G1_cnt[1] # !G1_cnt[0];

--G1L12 is kbscan:inst6|col[0]~35
--operation mode is normal

G1L12 = !G1_cnt[1] # !G1_cnt[0];


--G1L9 is kbscan:inst6|col[0]~32
--operation mode is normal

G1L9 = G1_cnt[0] # !G1_cnt[1];

--G1L13 is kbscan:inst6|col[0]~36
--operation mode is normal

G1L13 = G1_cnt[0] # !G1_cnt[1];


--G1L10 is kbscan:inst6|col[0]~33
--operation mode is normal

G1L10 = G1_cnt[1] # !G1_cnt[0];

--G1L14 is kbscan:inst6|col[0]~37
--operation mode is normal

G1L14 = G1_cnt[1] # !G1_cnt[0];


--G1L11 is kbscan:inst6|col[0]~34
--operation mode is normal

G1L11 = G1_cnt[0] # G1_cnt[1];

--G1L15 is kbscan:inst6|col[0]~38
--operation mode is normal

G1L15 = G1_cnt[0] # G1_cnt[1];


--K2_q[7] is lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[7]
K2_q[7]_clock_0 = clk;
K2_q[7]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[7]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[7] = MEMORY_SEGMENT(, , K2_q[7]_clock_0, , , , , , K2_q[7]_write_address, K2_q[7]_read_address);


--K1_q[7] is lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[7]
K1_q[7]_clock_0 = clk;
K1_q[7]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[7]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[7] = MEMORY_SEGMENT(, , K1_q[7]_clock_0, , , , , , K1_q[7]_write_address, K1_q[7]_read_address);


--K3_q[7] is lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[7]
K3_q[7]_clock_0 = clk;
K3_q[7]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K3_q[7]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K3_q[7] = MEMORY_SEGMENT(, , K3_q[7]_clock_0, , , , , , K3_q[7]_write_address, K3_q[7]_read_address);


--H1L18 is selec:inst8|bo_xing~56
--operation mode is normal

H1L18 = bo_select[0] & (bo_select[1]) # !bo_select[0] & (bo_select[1] & K1_q[7] # !bo_select[1] & (K3_q[7]));

--H1L26 is selec:inst8|bo_xing~80
--operation mode is normal

H1L26 = bo_select[0] & (bo_select[1]) # !bo_select[0] & (bo_select[1] & K1_q[7] # !bo_select[1] & (K3_q[7]));


--K1_q[6] is lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[6]
K1_q[6]_clock_0 = clk;
K1_q[6]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[6]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[6] = MEMORY_SEGMENT(, , K1_q[6]_clock_0, , , , , , K1_q[6]_write_address, K1_q[6]_read_address);


--K2_q[6] is lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[6]
K2_q[6]_clock_0 = clk;
K2_q[6]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[6]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[6] = MEMORY_SEGMENT(, , K2_q[6]_clock_0, , , , , , K2_q[6]_write_address, K2_q[6]_read_address);


--K3_q[6] is lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[6]
K3_q[6]_clock_0 = clk;
K3_q[6]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K3_q[6]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K3_q[6] = MEMORY_SEGMENT(, , K3_q[6]_clock_0, , , , , , K3_q[6]_write_address, K3_q[6]_read_address);


--H1L19 is selec:inst8|bo_xing~58
--operation mode is normal

H1L19 = bo_select[1] & (bo_select[0]) # !bo_select[1] & (bo_select[0] & K2_q[6] # !bo_select[0] & (K3_q[6]));

--H1L27 is selec:inst8|bo_xing~81
--operation mode is normal

H1L27 = bo_select[1] & (bo_select[0]) # !bo_select[1] & (bo_select[0] & K2_q[6] # !bo_select[0] & (K3_q[6]));


--K2_q[5] is lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[5]
K2_q[5]_clock_0 = clk;
K2_q[5]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[5]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[5] = MEMORY_SEGMENT(, , K2_q[5]_clock_0, , , , , , K2_q[5]_write_address, K2_q[5]_read_address);


--K1_q[5] is lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[5]
K1_q[5]_clock_0 = clk;
K1_q[5]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[5]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[5] = MEMORY_SEGMENT(, , K1_q[5]_clock_0, , , , , , K1_q[5]_write_address, K1_q[5]_read_address);


--K3_q[5] is lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[5]
K3_q[5]_clock_0 = clk;
K3_q[5]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K3_q[5]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K3_q[5] = MEMORY_SEGMENT(, , K3_q[5]_clock_0, , , , , , K3_q[5]_write_address, K3_q[5]_read_address);


--H1L20 is selec:inst8|bo_xing~60
--operation mode is normal

H1L20 = bo_select[0] & (bo_select[1]) # !bo_select[0] & (bo_select[1] & K1_q[5] # !bo_select[1] & (K3_q[5]));

--H1L28 is selec:inst8|bo_xing~82
--operation mode is normal

H1L28 = bo_select[0] & (bo_select[1]) # !bo_select[0] & (bo_select[1] & K1_q[5] # !bo_select[1] & (K3_q[5]));


--K1_q[4] is lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[4]
K1_q[4]_clock_0 = clk;
K1_q[4]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[4]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[4] = MEMORY_SEGMENT(, , K1_q[4]_clock_0, , , , , , K1_q[4]_write_address, K1_q[4]_read_address);


--K2_q[4] is lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[4]
K2_q[4]_clock_0 = clk;
K2_q[4]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[4]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[4] = MEMORY_SEGMENT(, , K2_q[4]_clock_0, , , , , , K2_q[4]_write_address, K2_q[4]_read_address);


--K3_q[4] is lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[4]
K3_q[4]_clock_0 = clk;
K3_q[4]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K3_q[4]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K3_q[4] = MEMORY_SEGMENT(, , K3_q[4]_clock_0, , , , , , K3_q[4]_write_address, K3_q[4]_read_address);


--H1L21 is selec:inst8|bo_xing~62
--operation mode is normal

H1L21 = bo_select[1] & (bo_select[0]) # !bo_select[1] & (bo_select[0] & K2_q[4] # !bo_select[0] & (K3_q[4]));

--H1L29 is selec:inst8|bo_xing~83
--operation mode is normal

H1L29 = bo_select[1] & (bo_select[0]) # !bo_select[1] & (bo_select[0] & K2_q[4] # !bo_select[0] & (K3_q[4]));


--K2_q[3] is lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[3]
K2_q[3]_clock_0 = clk;
K2_q[3]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[3]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[3] = MEMORY_SEGMENT(, , K2_q[3]_clock_0, , , , , , K2_q[3]_write_address, K2_q[3]_read_address);


--K1_q[3] is lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[3]
K1_q[3]_clock_0 = clk;
K1_q[3]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[3]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[3] = MEMORY_SEGMENT(, , K1_q[3]_clock_0, , , , , , K1_q[3]_write_address, K1_q[3]_read_address);


--K3_q[3] is lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[3]
K3_q[3]_clock_0 = clk;
K3_q[3]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K3_q[3]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K3_q[3] = MEMORY_SEGMENT(, , K3_q[3]_clock_0, , , , , , K3_q[3]_write_address, K3_q[3]_read_address);


--H1L22 is selec:inst8|bo_xing~64
--operation mode is normal

H1L22 = bo_select[0] & (bo_select[1]) # !bo_select[0] & (bo_select[1] & K1_q[3] # !bo_select[1] & (K3_q[3]));

--H1L30 is selec:inst8|bo_xing~84
--operation mode is normal

H1L30 = bo_select[0] & (bo_select[1]) # !bo_select[0] & (bo_select[1] & K1_q[3] # !bo_select[1] & (K3_q[3]));


--K1_q[2] is lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[2]
K1_q[2]_clock_0 = clk;
K1_q[2]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[2]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K1_q[2] = MEMORY_SEGMENT(, , K1_q[2]_clock_0, , , , , , K1_q[2]_write_address, K1_q[2]_read_address);


--K2_q[2] is lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[2]
K2_q[2]_clock_0 = clk;
K2_q[2]_write_address = WR_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[2]_read_address = RD_ADDR(C1_address[0], C1_address[1], C1_address[2], C1_address[3], C1_address[4], C1_address[5], C1_address[6], C1_address[7]);
K2_q[2] = MEMORY_SEGMENT(, , K2_q[2]_clock_0, , , , , , K2_q[2]_write_address, K2_q[2]_read_address);