📄 dds.sim.rpt
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+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 66.67 % ;
; Total nodes checked ; 117 ;
; Total output ports checked ; 114 ;
; Total output ports with complete 1/0-value coverage ; 76 ;
; Total output ports with no 1/0-value coverage ; 35 ;
; Total output ports with no 1-value coverage ; 35 ;
; Total output ports with no 0-value coverage ; 38 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; |boxing|kbscan:inst6|col[0]~31 ; |boxing|kbscan:inst6|col[0]~31 ; data_out0 ;
; |boxing|kbscan:inst6|col[0]~32 ; |boxing|kbscan:inst6|col[0]~32 ; data_out0 ;
; |boxing|kbscan:inst6|col[0]~33 ; |boxing|kbscan:inst6|col[0]~33 ; data_out0 ;
; |boxing|kbscan:inst6|col[0]~34 ; |boxing|kbscan:inst6|col[0]~34 ; data_out0 ;
; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[7] ; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[7] ; dataout ;
; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[7] ; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[7] ; dataout ;
; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[7] ; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[7] ; dataout ;
; |boxing|selec:inst8|bo_xing~56 ; |boxing|selec:inst8|bo_xing~56 ; data_out0 ;
; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[6] ; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[6] ; dataout ;
; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[6] ; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[6] ; dataout ;
; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[6] ; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[6] ; dataout ;
; |boxing|selec:inst8|bo_xing~58 ; |boxing|selec:inst8|bo_xing~58 ; data_out0 ;
; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[5] ; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[5] ; dataout ;
; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[5] ; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[5] ; dataout ;
; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[5] ; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[5] ; dataout ;
; |boxing|selec:inst8|bo_xing~60 ; |boxing|selec:inst8|bo_xing~60 ; data_out0 ;
; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[4] ; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[4] ; dataout ;
; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[4] ; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[4] ; dataout ;
; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[4] ; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[4] ; dataout ;
; |boxing|selec:inst8|bo_xing~62 ; |boxing|selec:inst8|bo_xing~62 ; data_out0 ;
; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[3] ; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[3] ; dataout ;
; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[3] ; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[3] ; dataout ;
; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[3] ; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[3] ; dataout ;
; |boxing|selec:inst8|bo_xing~64 ; |boxing|selec:inst8|bo_xing~64 ; data_out0 ;
; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[2] ; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[2] ; dataout ;
; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[2] ; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[2] ; dataout ;
; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[2] ; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[2] ; dataout ;
; |boxing|selec:inst8|bo_xing~66 ; |boxing|selec:inst8|bo_xing~66 ; data_out0 ;
; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[1] ; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[1] ; dataout ;
; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1] ; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[1] ; dataout ;
; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1] ; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[1] ; dataout ;
; |boxing|selec:inst8|bo_xing~68 ; |boxing|selec:inst8|bo_xing~68 ; data_out0 ;
; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[0] ; |boxing|lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom|q[0] ; dataout ;
; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[0] ; |boxing|lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom|q[0] ; dataout ;
; |boxing|selec:inst8|bo_xing~70 ; |boxing|selec:inst8|bo_xing~70 ; data_out0 ;
; |boxing|kbscan:inst6|add~14 ; |boxing|kbscan:inst6|add~14 ; data_out0 ;
; |boxing|kbscan:inst6|Mux~666 ; |boxing|kbscan:inst6|Mux~666 ; data_out0 ;
; |boxing|pin:inst1|address[0] ; |boxing|pin:inst1|address[0] ; data_out0 ;
; |boxing|pin:inst1|address[1] ; |boxing|pin:inst1|address[1] ; data_out0 ;
; |boxing|pin:inst1|address[2] ; |boxing|pin:inst1|address[2] ; data_out0 ;
; |boxing|pin:inst1|address[3] ; |boxing|pin:inst1|address[3] ; data_out0 ;
; |boxing|pin:inst1|address[4] ; |boxing|pin:inst1|address[4] ; data_out0 ;
; |boxing|pin:inst1|address[5] ; |boxing|pin:inst1|address[5] ; data_out0 ;
; |boxing|pin:inst1|address[6] ; |boxing|pin:inst1|address[6] ; data_out0 ;
; |boxing|pin:inst1|address[7] ; |boxing|pin:inst1|address[7] ; data_out0 ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; data_out0 ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; data_out0 ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] ; cout ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; data_out0 ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; data_out0 ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] ; cout ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; data_out0 ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] ; cout ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; data_out0 ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] ; cout ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0 ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] ; cout ;
; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[7] ; |boxing|pin:inst1|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[7] ; data_out0 ;
; |boxing|clk ; |boxing|clk ; dataout ;
; |boxing|start ; |boxing|start ; dataout ;
; |boxing|cs4 ; |boxing|cs4 ; padio ;
; |boxing|bo_xing[7] ; |boxing|bo_xing[7] ; padio ;
; |boxing|bo_xing[6] ; |boxing|bo_xing[6] ; padio ;
; |boxing|bo_xing[5] ; |boxing|bo_xing[5] ; padio ;
; |boxing|bo_xing[4] ; |boxing|bo_xing[4] ; padio ;
; |boxing|bo_xing[3] ; |boxing|bo_xing[3] ; padio ;
; |boxing|bo_xing[2] ; |boxing|bo_xing[2] ; padio ;
; |boxing|bo_xing[1] ; |boxing|bo_xing[1] ; padio ;
; |boxing|bo_xing[0] ; |boxing|bo_xing[0] ; padio ;
; |boxing|col[3] ; |boxing|col[3] ; padio ;
; |boxing|col[2] ; |boxing|col[2] ; padio ;
; |boxing|col[1] ; |boxing|col[1] ; padio ;
; |boxing|col[0] ; |boxing|col[0] ; padio ;
; |boxing|cs4~0 ; |boxing|cs4~0 ; data_out0 ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+------------------------------------------------------------------------+------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+------------------------------------------------------------------------+------------------------------------------------------------------------+------------------+
; |boxing|kbscan:inst6|int0~3 ; |boxing|kbscan:inst6|int0~3 ; data_out0 ;
; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[0] ; |boxing|lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom|q[0] ; dataout ;
; |boxing|rtl~20 ; |boxing|rtl~20 ; data_out0 ;
; |boxing|kbscan:inst6|Mux~664 ; |boxing|kbscan:inst6|Mux~664 ; data_out0 ;
; |boxing|kbscan:inst6|Mux~665 ; |boxing|kbscan:inst6|Mux~665 ; data_out0 ;
; |boxing|kbscan:inst6|Mux~668 ; |boxing|kbscan:inst6|Mux~668 ; data_out0 ;
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