dds.map.rpt

文件夹里面有两个文件

; DEVICE_FAMILY                      ; FLEX10K      ; Untyped                                ;
; CBXI_PARAMETER                     ; NOTHING      ; Untyped                                ;
+------------------------------------+--------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: pin:inst1|lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+-------------------------------------------+
; Parameter Name         ; Value       ; Type                                      ;
+------------------------+-------------+-------------------------------------------+
; LPM_WIDTH              ; 8           ; Untyped                                   ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                   ;
; LPM_DIRECTION          ; ADD         ; Untyped                                   ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                   ;
; LPM_PIPELINE           ; 0           ; Untyped                                   ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                   ;
; REGISTERED_AT_END      ; 0           ; Untyped                                   ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                   ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                   ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                   ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                        ;
; DEVICE_FAMILY          ; FLEX10K     ; Untyped                                   ;
; USE_WYS                ; OFF         ; Untyped                                   ;
; STYLE                  ; FAST        ; Untyped                                   ;
; CBXI_PARAMETER         ; add_sub_rjh ; Untyped                                   ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                              ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                              ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                            ;
+------------------------+-------------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/dds/dds.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Jan 09 08:02:44 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds
Info: Found 2 design units, including 1 entities, in source file kbscan.vhd
    Info: Found design unit 1: kbscan-behave
    Info: Found entity 1: kbscan
Info: Found 1 design units, including 1 entities, in source file boxing.bdf
    Info: Found entity 1: boxing
Info: Found 2 design units, including 1 entities, in source file selec.vhd
    Info: Found design unit 1: selec-xuanze
    Info: Found entity 1: selec
Info: Found 2 design units, including 1 entities, in source file pin.vhd
    Info: Found design unit 1: pin-pinlv
    Info: Found entity 1: pin
Info: Found 1 design units, including 1 entities, in source file out.bdf
    Info: Found entity 1: out
Info: Found 2 design units, including 1 entities, in source file pass.vhd
    Info: Found design unit 1: pass-behave
    Info: Found entity 1: pass
Info: Elaborating entity "boxing" for the top level hierarchy
Info: Elaborating entity "kbscan" for hierarchy "kbscan:inst6"
Warning (10492): VHDL Process Statement warning at kbscan.vhd(32): signal "row" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at kbscan.vhd(41): signal "row" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at kbscan.vhd(50): signal "row" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at kbscan.vhd(59): signal "row" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "selec" for hierarchy "selec:inst8"
Warning: Using design file lpm_rom3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_rom3-SYN
    Info: Found entity 1: lpm_rom3
Info: Elaborating entity "lpm_rom3" for hierarchy "lpm_rom3:inst4"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom3:inst4|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altrom.tdf
    Info: Found entity 1: altrom
Info: Elaborating entity "altrom" for hierarchy "lpm_rom3:inst4|altsyncram:altsyncram_component|altrom:rom"
Info: Elaborating entity "pin" for hierarchy "pin:inst1"
Info: Elaborating entity "pass" for hierarchy "pass:inst2"
Warning: Using design file lpm_rom1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_rom1-SYN
    Info: Found entity 1: lpm_rom1
Info: Elaborating entity "lpm_rom1" for hierarchy "lpm_rom1:inst3"
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom1:inst3|altsyncram:altsyncram_component"
Info: Elaborating entity "altrom" for hierarchy "lpm_rom1:inst3|altsyncram:altsyncram_component|altrom:rom"
Warning: Using design file lpm_rom0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_rom0-SYN
    Info: Found entity 1: lpm_rom0
Info: Elaborating entity "lpm_rom0" for hierarchy "lpm_rom0:inst"
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component"
Info: Elaborating entity "altrom" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component|altrom:rom"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Duplicate registers merged to single register
    Info: Duplicate register "pin:inst1|address_reg[0]" merged to single register "pin:inst1|address[0]"
    Info: Duplicate register "pin:inst1|address_reg[1]" merged to single register "pin:inst1|address[1]"
    Info: Duplicate register "pin:inst1|address_reg[2]" merged to single register "pin:inst1|address[2]"
    Info: Duplicate register "pin:inst1|address_reg[3]" merged to single register "pin:inst1|address[3]"
    Info: Duplicate register "pin:inst1|address_reg[4]" merged to single register "pin:inst1|address[4]"
    Info: Duplicate register "pin:inst1|address_reg[5]" merged to single register "pin:inst1|address[5]"
    Info: Duplicate register "pin:inst1|address_reg[6]" merged to single register "pin:inst1|address[6]"
    Info: Duplicate register "pin:inst1|address_reg[7]" merged to single register "pin:inst1|address[7]"
Info: Implemented 115 device resources after synthesis - the final resource count might be different
    Info: Implemented 16 input pins
    Info: Implemented 18 output pins
    Info: Implemented 57 logic cells
    Info: Implemented 24 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Processing ended: Wed Jan 09 08:02:53 2008
    Info: Elapsed time: 00:00:09