reg_m55800.h

AN-1155.zip ucos在AT91M5800上的一直 编译器为IAR

#define US0_RTOR    (USART0_BASE->US_RTOR)
#define US1_RTOR    (USART1_BASE->US_RTOR)
#define US2_RTOR    (USART2_BASE->US_RTOR)

#define US0_TTGR    (USART0_BASE->US_TTGR)
#define US1_TTGR    (USART1_BASE->US_TTGR)
#define US2_TTGR    (USART2_BASE->US_TTGR)

#define US0_RPR     (USART0_BASE->US_RPR)
#define US1_RPR     (USART1_BASE->US_RPR)
#define US2_RPR     (USART2_BASE->US_RPR)

#define US0_RCR     (USART0_BASE->US_RCR)
#define US1_RCR     (USART1_BASE->US_RCR)
#define US2_RCR     (USART2_BASE->US_RCR)

#define US0_TPR     (USART0_BASE->US_TPR)
#define US1_TPR     (USART1_BASE->US_TPR)
#define US2_TPR     (USART2_BASE->US_TPR)

#define US0_TCR     (USART0_BASE->US_TCR)
#define US1_TCR     (USART1_BASE->US_TCR)
#define US2_TCR     (USART2_BASE->US_TCR)

/*-------------------------*/
/* Timer Counter Registers */
/*-------------------------*/

#define TC0_BASE    (TCB0_BASE->TC[0])
#define TC1_BASE    (TCB0_BASE->TC[1])
#define TC2_BASE    (TCB0_BASE->TC[2])
#define TC3_BASE    (TCB1_BASE->TC[0])
#define TC4_BASE    (TCB1_BASE->TC[1])
#define TC5_BASE    (TCB1_BASE->TC[2])

#define TC0_BCR     (TCB0_BASE->TC_BCR)
#define TC1_BCR     (TCB0_BASE->TC_BCR)
#define TC2_BCR     (TCB0_BASE->TC_BCR)
#define TC3_BCR     (TCB1_BASE->TC_BCR)
#define TC4_BCR     (TCB1_BASE->TC_BCR)
#define TC5_BCR     (TCB1_BASE->TC_BCR)

#define TC0_BMR     (TCB0_BASE->TC_BMR)
#define TC1_BMR     (TCB0_BASE->TC_BMR)
#define TC2_BMR     (TCB0_BASE->TC_BMR)
#define TC3_BMR     (TCB1_BASE->TC_BMR)
#define TC4_BMR     (TCB1_BASE->TC_BMR)
#define TC5_BMR     (TCB1_BASE->TC_BMR)

#define TC0_CCR     (TC0_BASE.TC_CCR)
#define TC0_CMR     (TC0_BASE.TC_CMR)
#define TC0_CV      (TC0_BASE.TC_CV)
#define TC0_RA      (TC0_BASE.TC_RA)
#define TC0_RB      (TC0_BASE.TC_RB)
#define TC0_RC      (TC0_BASE.TC_RC)
#define TC0_SR      (TC0_BASE.TC_SR)
#define TC0_IER     (TC0_BASE.TC_IER)
#define TC0_IDR     (TC0_BASE.TC_IDR)
#define TC0_IMR     (TC0_BASE.TC_IMR)

#define TC1_CCR     (TC1_BASE.TC_CCR)
#define TC1_CMR     (TC1_BASE.TC_CMR)
#define TC1_CV      (TC1_BASE.TC_CV)
#define TC1_RA      (TC1_BASE.TC_RA)
#define TC1_RB      (TC1_BASE.TC_RB)
#define TC1_RC      (TC1_BASE.TC_RC)
#define TC1_SR      (TC1_BASE.TC_SR)
#define TC1_IER     (TC1_BASE.TC_IER)
#define TC1_IDR     (TC1_BASE.TC_IDR)
#define TC1_IMR     (TC1_BASE.TC_IMR)

#define TC2_CCR     (TC2_BASE.TC_CCR)
#define TC2_CMR     (TC2_BASE.TC_CMR)
#define TC2_CV      (TC2_BASE.TC_CV)
#define TC2_RA      (TC2_BASE.TC_RA)
#define TC2_RB      (TC2_BASE.TC_RB)
#define TC2_RC      (TC2_BASE.TC_RC)
#define TC2_SR      (TC2_BASE.TC_SR)
#define TC2_IER     (TC2_BASE.TC_IER)
#define TC2_IDR     (TC2_BASE.TC_IDR)
#define TC2_IMR     (TC2_BASE.TC_IMR)

#define TC3_CCR     (TC3_BASE.TC_CCR)
#define TC3_CMR     (TC3_BASE.TC_CMR)
#define TC3_CV      (TC3_BASE.TC_CV)
#define TC3_RA      (TC3_BASE.TC_RA)
#define TC3_RB      (TC3_BASE.TC_RB)
#define TC3_RC      (TC3_BASE.TC_RC)
#define TC3_SR      (TC3_BASE.TC_SR)
#define TC3_IER     (TC3_BASE.TC_IER)
#define TC3_IDR     (TC3_BASE.TC_IDR)
#define TC3_IMR     (TC3_BASE.TC_IMR)

#define TC4_CCR     (TC4_BASE.TC_CCR)
#define TC4_CMR     (TC4_BASE.TC_CMR)
#define TC4_CV      (TC4_BASE.TC_CV)
#define TC4_RA      (TC4_BASE.TC_RA)
#define TC4_RB      (TC4_BASE.TC_RB)
#define TC4_RC      (TC4_BASE.TC_RC)
#define TC4_SR      (TC4_BASE.TC_SR)
#define TC4_IER     (TC4_BASE.TC_IER)
#define TC4_IDR     (TC4_BASE.TC_IDR)
#define TC4_IMR     (TC4_BASE.TC_IMR)

#define TC5_CCR     (TC5_BASE.TC_CCR)
#define TC5_CMR     (TC5_BASE.TC_CMR)
#define TC5_CV      (TC5_BASE.TC_CV)
#define TC5_RA      (TC5_BASE.TC_RA)
#define TC5_RB      (TC5_BASE.TC_RB)
#define TC5_RC      (TC5_BASE.TC_RC)
#define TC5_SR      (TC5_BASE.TC_SR)
#define TC5_IER     (TC5_BASE.TC_IER)
#define TC5_IDR     (TC5_BASE.TC_IDR)
#define TC5_IMR     (TC5_BASE.TC_IMR)


/*----------------------------*/
/* Real Time Clock Registers  */
/*----------------------------*/

#define RTC_CR      (RTC_BASE->RTC_CR)
#define RTC_MR      (RTC_BASE->RTC_MR)
#define RTC_TIMR    (RTC_BASE->RTC_TIMR)
#define RTC_CALR    (RTC_BASE->RTC_CALR)
#define RTC_TAR     (RTC_BASE->RTC_TAR)
#define RTC_CAR     (RTC_BASE->RTC_CAR)
#define RTC_SR      (RTC_BASE->RTC_SR)
#define RTC_SCCR    (RTC_BASE->RTC_SCCR)

#define RTC_IER     (RTC_BASE->RTC_IER)
#define RTC_IDR     (RTC_BASE->RTC_IDR)
#define RTC_IMR     (RTC_BASE->RTC_IMR)
#define RTC_VER     (RTC_BASE->RTC_VER)


/*---------------------------------------*/
/* Serial Peripheral Interface Registers */
/*---------------------------------------*/

#define SPI_CR      (SPI_BASE->SP_CR)
#define SPI_MR      (SPI_BASE->SP_MR)
#define SPI_RDR     (SPI_BASE->SP_RDR)
#define SPI_TDR     (SPI_BASE->SP_TDR)
#define SPI_SR      (SPI_BASE->SP_SR)

#define SPI_IER     (SPI_BASE->SP_IER)
#define SPI_IDR     (SPI_BASE->SP_IDR)
#define SPI_IMR     (SPI_BASE->SP_IMR)

#define SPI_RPR     (SPI_BASE->SP_RPR)
#define SPI_RCR     (SPI_BASE->SP_RCR)
#define SPI_TPR     (SPI_BASE->SP_TPR)
#define SPI_TCR     (SPI_BASE->SP_TCR)

#define SPI_CSR0    (SPI_BASE->SP_CSR[0])
#define SPI_CSR1    (SPI_BASE->SP_CSR[1])
#define SPI_CSR2    (SPI_BASE->SP_CSR[2])
#define SPI_CSR3    (SPI_BASE->SP_CSR[3])

/*-----------------------*/
/* DAC 0 and 1 Registers */
/*-----------------------*/

#define DAC0_CR      (DAC0_BASE->DAC_CR)
#define DAC1_CR      (DAC1_BASE->DAC_CR)

#define DAC0_MR      (DAC0_BASE->DAC_MR)
#define DAC1_MR      (DAC1_BASE->DAC_MR)

#define DAC0_DHR     (DAC0_BASE->DAC_DHR)
#define DAC1_DHR     (DAC1_BASE->DAC_DHR)

#define DAC0_DOR     (DAC0_BASE->DAC_DOR)
#define DAC1_DOR     (DAC1_BASE->DAC_DOR)

#define DAC0_SR      (DAC0_BASE->DAC_SR)
#define DAC1_SR      (DAC1_BASE->DAC_SR)

#define DAC0_IER     (DAC0_BASE->DAC_IER)
#define DAC1_IER     (DAC1_BASE->DAC_IER)

#define DAC0_IDR     (DAC0_BASE->DAC_IDR)
#define DAC1_IDR     (DAC1_BASE->DAC_IDR)

#define DAC0_IMR     (DAC0_BASE->DAC_IMR)
#define DAC1_IMR     (DAC1_BASE->DAC_IMR)

/*-----------------------*/
/* ADC 0 and 1 Registers */
/*-----------------------*/
#define ADC0_CR      (ADC0_BASE->ADC_CR)
#define ADC1_CR      (ADC1_BASE->ADC_CR)

#define ADC0_MR      (ADC0_BASE->ADC_MR)
#define ADC1_MR      (ADC1_BASE->ADC_MR)

#define ADC0_CHER    (ADC0_BASE->ADC_CHER)
#define ADC1_CHER    (ADC1_BASE->ADC_CHER)

#define ADC0_CHDR    (ADC0_BASE->ADC_CHDR)
#define ADC1_CHDR    (ADC1_BASE->ADC_CHDR)

#define ADC0_CHSR    (ADC0_BASE->ADC_CHSR)
#define ADC1_CHSR    (ADC1_BASE->ADC_CHSR)

#define ADC0_SR      (ADC0_BASE->ADC_SR)
#define ADC1_SR      (ADC1_BASE->ADC_SR)

#define ADC0_IER     (ADC0_BASE->ADC_IER)
#define ADC1_IER     (ADC1_BASE->ADC_IER)

#define ADC0_IDR     (ADC0_BASE->ADC_IDR)
#define ADC1_IDR     (ADC1_BASE->ADC_IDR)

#define ADC0_IMR     (ADC0_BASE->ADC_IMR)
#define ADC1_IMR     (ADC1_BASE->ADC_IMR)

#define ADC0_CDR0    (ADC0_BASE->ADC_CDR0)
#define ADC1_CDR0    (ADC1_BASE->ADC_CDR0)

#define ADC0_CDR1    (ADC0_BASE->ADC_CDR1)
#define ADC1_CDR1    (ADC1_BASE->ADC_CDR1)

#define ADC0_CDR2    (ADC0_BASE->ADC_CDR2)
#define ADC1_CDR2    (ADC1_BASE->ADC_CDR2)

#define ADC0_CDR3    (ADC0_BASE->ADC_CDR3)
#define ADC1_CDR3    (ADC1_BASE->ADC_CDR3)

/*-----------*/
/* Watchdog  */
/*-----------*/
#define WD_OMR      (WD_BASE->WD_OMR)
#define WD_CMR      (WD_BASE->WD_CMR)
#define WD_CR       (WD_BASE->WD_CR)


#endif /* reg_m55800_h */