📄 watchdog2.lst
字号:
ARM COMPILER V2.40c, watchdog2 08/10/05 18:14:14 PAGE 1
ARM COMPILER V2.40c, COMPILATION OF MODULE watchdog2
OBJECT MODULE PLACED IN watchdog2.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe watchdog2.c THUMB DEBUG TABS(4)
stmt level source
1 /*********************************************************************
2
3 Author : ADI - Apps www.analog.com/MicroConverter
4
5 Date : Sept. 2005
6
7 File : Watchdog2.c
8
9 Hardware : Applicable to ADuC702x rev H or I silicon
10 Currently targetting ADuC7026.
11
12 Description : This example demonstrates the use of the watchdog timer in secure mode
13 - on the four first occurences the timer is refreshed/reloaded on time
14 with the correct seed
15 - on the fifth occurence:
16 OPTION 0: the seed is incorrect, the timer resets the part straigh away.
17 OPTION 1: code is delayed, the timer will time out before resetting the part.
18
19 *********************************************************************/
20 #include<ADuC7026.h>
21
22
23 /*------------ options ------------
24 OPTION=0: incorrect seed
25 OPTION=1: too late
26 ----------------------------------------------*/
27 #define OPTION 0
28
29
30
31 void delay (int length)
32 {
33 1 while (length >=0)
34 1 length--;
35 1 }
36
37 char seed;
38 char poly = 0xB1;
39
40 void delay(int);
41
42
43 int main(void)
44 {
45 1 char i;
46 1 seed = 0xAA; // Setting seed initial value
47 1
48 1 GP4DAT = 0x04000000; // P4.2 configured as an output. LED is turned on
49 1 GP1DAT = 0x01000000; // P1.0 as output
50 1
51 1 T3CLRI = seed;
52 1 delay(0x10); // 0.35ms
53 1 T3LD = 0x1000; // 125ms
54 1 T3CON = 0xF0; // IRQ instead of reset, for test purposes only
55 1
56 1 while (1)
57 1 {
58 2
59 2 for (i=0;i<4;i++){
ARM COMPILER V2.40c, watchdog2 08/10/05 18:14:14 PAGE 2
60 3 delay (0x30000);
61 3 T3CLRI = seed;
62 3 GP4DAT ^= 0x00040000;
63 3 if ((seed & 0x80)==0x80) seed = ((seed ^ poly)<<1) + 1 ; // Generating next seed...
64 3 else seed = (seed <<1); // ...value in sequence
65 3 }
66 2
67 2 if (OPTION == 0) T3CLRI = 0x00; // Not part of sequence, will cause immediate reset.
68 2 if (OPTION == 1){ // Delay greater than Timer3 value so will cause reset
69 3 delay(0xA0000); // > 125ms and so will cause a reset.
70 3 T3CLRI = seed;
71 3 }
72 2
73 2 }
74 1 }
ARM COMPILER V2.40c, watchdog2 08/10/05 18:14:14 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC delay?T
PUBLIC main
PUBLIC seed
PUBLIC poly
*** DATA SEGMENT '?DT0?watchdog2':
00000000 seed:
00000000 DS 1
00000001 poly:
00000001 BEGIN_INIT
00000001 B1 DB 0xB1
00000002 END_INIT
*** CODE SEGMENT '?PR?delay?T?watchdog2':
40: void delay(int);
00000000 ---- Variable 'length' assigned to Register 'R0' ----
00000000 E000 B L_1 ; T=0x00000004
00000002 L_3:
00000002 3801 SUB R0,#0x1
00000004 L_1:
00000004 1C01 MOV R1,R0 ; length
00000006 2900 CMP R1,#0x0 ; length
00000008 DAFB BGE L_3 ; T=0x00000002
0000000A 4770 BX R14
0000000C ENDP ; 'delay?T'
*** CODE SEGMENT '?PR?main?watchdog2':
43: int main(void)
00000000 B500 PUSH {LR}
44: {
00000002 ; SCOPE-START
46: seed = 0xAA; // Setting seed initial value
00000002 21AA MOV R1,#0xAA
00000004 4800 LDR R0,=seed ; seed
00000006 7001 STRB R1,[R0,#0x0] ; seed
48: GP4DAT = 0x04000000; // P4.2 configured as an output. LED is turned on
00000008 4800 LDR R1,=0x4000000
0000000A 4800 LDR R0,=0xFFFFF460
0000000C 6001 STR R1,[R0,#0x0]
49: GP1DAT = 0x01000000; // P1.0 as output
0000000E 4800 LDR R1,=0x1000000
00000010 4800 LDR R0,=0xFFFFF430
00000012 6001 STR R1,[R0,#0x0]
51: T3CLRI = seed;
00000014 4800 LDR R0,=seed ; seed
00000016 7800 LDRB R0,[R0,#0x0] ; seed
00000018 1C01 MOV R1,R0
0000001A 4800 LDR R0,=0xFFFF036C
0000001C 6001 STR R1,[R0,#0x0]
52: delay(0x10); // 0.35ms
0000001E 2010 MOV R0,#0x10
00000020 F7FF BL delay?T ; T=0x0001 (1)
00000022 FFEE BL delay?T ; T=0x0001 (2)
53: T3LD = 0x1000; // 125ms
00000024 4800 LDR R1,=0x1000
00000026 4800 LDR R0,=0xFFFF0360
00000028 6001 STR R1,[R0,#0x0]
54: T3CON = 0xF0; // IRQ instead of reset, for test purposes only
0000002A 21F0 MOV R1,#0xF0
0000002C 4800 LDR R0,=0xFFFF0368
ARM COMPILER V2.40c, watchdog2 08/10/05 18:14:14 PAGE 4
0000002E 6001 STR R1,[R0,#0x0]
59: for (i=0;i<4;i++){
00000030 L_13:
00000030 2200 MOV R2,#0x0
00000032 ---- Variable 'i' assigned to Register 'R2' ----
00000032 E023 B L_11 ; T=0x0000007C
00000034 L_12:
60: delay (0x30000);
00000034 4800 LDR R0,=0x30000
00000036 F7FF BL delay?T ; T=0x0001 (1)
00000038 FFE3 BL delay?T ; T=0x0001 (2)
61: T3CLRI = seed;
0000003A 4800 LDR R0,=seed ; seed
0000003C 7800 LDRB R0,[R0,#0x0] ; seed
0000003E 1C03 MOV R3,R0
00000040 4800 LDR R1,=0xFFFF036C
00000042 600B STR R3,[R1,#0x0]
62: GP4DAT ^= 0x00040000;
00000044 4800 LDR R4,=0x40000
00000046 4800 LDR R1,=0xFFFFF460
00000048 680B LDR R3,[R1,#0x0]
0000004A 4063 EOR R3,R4
0000004C 600B STR R3,[R1,#0x0]
63: if ((seed & 0x80)==0x80) seed = ((seed ^ poly)<<1) + 1 ; // Generating next seed...
0000004E 1C01 MOV R1,R0
00000050 2080 MOV R0,#0x80
00000052 4201 TST R1,R0
00000054 D00A BEQ L_14 ; T=0x0000006C
00000056 4800 LDR R0,=poly ; poly
00000058 7800 LDRB R0,[R0,#0x0] ; poly
0000005A 1C03 MOV R3,R0
0000005C 404B EOR R3,R1
0000005E 005B LSL R3,R3,#0x1
00000060 3301 ADD R3,#0x1
00000062 061B LSL R3,R3,#0x18
00000064 0E1B LSR R3,R3,#0x18
00000066 4800 LDR R0,=seed ; seed
00000068 7003 STRB R3,[R0,#0x0] ; seed
0000006A E004 B L_9 ; T=0x00000076
0000006C L_14:
64: else seed = (seed <<1); // ...value in sequence
0000006C 0049 LSL R1,R1,#0x1
0000006E 0609 LSL R1,R1,#0x18
00000070 0E09 LSR R1,R1,#0x18
00000072 4800 LDR R0,=seed ; seed
00000074 7001 STRB R1,[R0,#0x0] ; seed
65: }
00000076 L_9:
00000076 3201 ADD R2,#0x1
00000078 0612 LSL R2,R2,#0x18
0000007A 0E12 LSR R2,R2,#0x18
0000007C L_11:
0000007C 1C10 MOV R0,R2 ; i
0000007E 0600 LSL R0,R0,#0x18 ; i
00000080 0E00 LSR R0,R0,#0x18
00000082 2804 CMP R0,#0x4
00000084 DBD6 BLT L_12 ; T=0x00000034
67: if (OPTION == 0) T3CLRI = 0x00; // Not part of sequence, will cause immediate reset.
00000086 2100 MOV R1,#0x0
00000088 4800 LDR R0,=0xFFFF036C
0000008A 6001 STR R1,[R0,#0x0]
68: if (OPTION == 1){ // Delay greater than Timer3 value so will cause reset
0000008C E7D0 B L_13 ; T=0x00000030
73: }
0000008E ; SCOPE-END
74: }
ARM COMPILER V2.40c, watchdog2 08/10/05 18:14:14 PAGE 5
0000008E BC08 POP {R3}
00000090 4718 BX R3
00000092 ENDP ; 'main'
Module Information Static
----------------------------------
code size = ------
data size = 2
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -