i2c_master.lst
来自「ADuC7020/26是ADI模拟公司开发的ARM7TDMI内核」· LST 代码 · 共 268 行
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268 行
ARM COMPILER V2.42, I2C_Master 09/01/06 14:42:27 PAGE 1
ARM COMPILER V2.42, COMPILATION OF MODULE I2C_Master
OBJECT MODULE PLACED IN I2C_Master.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe I2C_Master.c THUMB DEBUG TABS(4)
stmt level source
1 /***************************************************************************
2
3 Author : ADI - Apps www.analog.com/MicroConverter
4
5 Date : Sept. 2005
6
7 File : I2C_Master.c
8
9 Hardware : Applicable to ADuC702x rev H or I silicon
10 Currently targetting ADuC7026.
11
12 Description : I2C master to demonstrate with I2C_Slave.c
13
14 Operates in two modes, read & write (called recieve and
15 transmit here). At the begining of an I2C transmission, the
16 Master sends an address. The LSB of this address determines
17 if the Master is to read (1) or write (0).
18
19
20 ***************************************************************************/
21
22 #include<ADuC7020.h>
23
24 void delay(int);
25 void IRQ_Handler() __irq;
26
27 #define count 0x4; // Number of bytes to be recieved - 1
28 int i = 0, dat[5]; // Size of dat should be (count + 1)
29
30
31 int main()
32 {
33 1
34 1 GP1CON = 0x22; // I2C on P1.0 and P1.1
35 1
36 1 I2C0CFG = 0x82; // Master Enable & Enable Generation of Master Clock
37 1
38 1 // I2C-Master setup
39 1 I2C0DIV = 0xCFCF; // 0x3232 = 400kHz
40 1 // 0xCFCF = 100kHz
41 1
42 1 IRQEN = 0x400; // I2C0 Master Interupt
43 1
44 1 // Transmit
45 1 I2C0ADR = 0xA0; // set i2c address (LSB = 0, Master Write)
46 1 I2C0MTX = 0x55; // send i2c byte address
47 1
48 1
49 1 delay(4000);
50 1
51 1 // Recieve
52 1 i = 0;
53 1 I2C0CNT = count; // Number of bytes to be read from slave
54 1 I2C0ADR = 0xA1; // set i2c address (LSB = 1, Master Read)
55 1
56 1 while (1)
57 1 {
58 2 };
59 1
ARM COMPILER V2.42, I2C_Master 09/01/06 14:42:27 PAGE 2
60 1 return 0;
61 1 }
62
63
64
65
66 void delay (int length)
67 {
68 1 while (length >0)
69 1 length--;
70 1 }
71
72
73
74 /*************************************************/
75 /*************************************************/
76 /************ IRQ Service Routine *************/
77 /*************************************************/
78 /*************************************************/
79
80 void IRQ_Handler() __irq
81 {
82 1 // Transmit
83 1 if(((I2C0MSTA & 0x4) == 0x4) && (i < 8)) // Master Transmit IRQ
84 1 {
85 2 i++; // Transmits numbers 1-8
86 2 I2C0MTX = i;
87 2 }
88 1
89 1
90 1 // Recieve
91 1 if((I2C0MSTA & 0x8) == 0x8) // Master Recieve IRQ
92 1 {
93 2 dat[i] = I2C0MRX;
94 2 i++;
95 2 }
96 1 }
ARM COMPILER V2.42, I2C_Master 09/01/06 14:42:27 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC delay?T
PUBLIC IRQ_Handler?A
PUBLIC main
PUBLIC i
PUBLIC dat
*** DATA SEGMENT '?DT0?I2C_Master':
00000000 i:
00000000 BEGIN_INIT
00000000 00000000 DD 0x0
00000004 END_INIT
00000004 dat:
00000004 DS 20
*** CODE SEGMENT '?PR?main?I2C_Master':
31: int main()
00000000 B500 PUSH {LR}
34: GP1CON = 0x22; // I2C on P1.0 and P1.1
00000002 2122 MOV R1,#0x22
00000004 4800 LDR R0,=0xFFFFF404
00000006 6001 STR R1,[R0,#0x0]
36: I2C0CFG = 0x82; // Master Enable & Enable Generation of Master Clock
00000008 2182 MOV R1,#0x82
0000000A 4800 LDR R0,=0xFFFF082C
0000000C 6001 STR R1,[R0,#0x0]
39: I2C0DIV = 0xCFCF; // 0x3232 = 400kHz
0000000E 4800 LDRH R1,=0xCFCF
00000010 4800 LDR R0,=0xFFFF0830
00000012 8001 STRH R1,[R0,#0x0]
42: IRQEN = 0x400; // I2C0 Master Interupt
00000014 4800 LDR R1,=0x400
00000016 4800 LDR R0,=0xFFFF0008
00000018 6001 STR R1,[R0,#0x0]
45: I2C0ADR = 0xA0; // set i2c address (LSB = 0, Master Write)
0000001A 21A0 MOV R1,#0xA0
0000001C 4800 LDR R0,=0xFFFF081C
0000001E 6001 STR R1,[R0,#0x0]
46: I2C0MTX = 0x55; // send i2c byte address
00000020 2155 MOV R1,#0x55
00000022 4800 LDR R0,=0xFFFF0814
00000024 6001 STR R1,[R0,#0x0]
49: delay(4000);
00000026 4800 LDR R0,=0xFA0
00000028 F7FF BL delay?T ; T=0x0001 (1)
0000002A FFEA BL delay?T ; T=0x0001 (2)
52: i = 0;
0000002C 2100 MOV R1,#0x0
0000002E 4800 LDR R0,=i ; i
00000030 6001 STR R1,[R0,#0x0] ; i
53: I2C0CNT = count; // Number of bytes to be read from slave
00000032 2104 MOV R1,#0x4
00000034 4800 LDR R0,=0xFFFF0818
00000036 6001 STR R1,[R0,#0x0]
54: I2C0ADR = 0xA1; // set i2c address (LSB = 1, Master Read)
00000038 21A1 MOV R1,#0xA1
0000003A 4800 LDR R0,=0xFFFF081C
0000003C 6001 STR R1,[R0,#0x0]
58: };
0000003E L_1:
ARM COMPILER V2.42, I2C_Master 09/01/06 14:42:27 PAGE 4
0000003E E7FE B L_1 ; T=0x0000003E
61: }
00000040 BC08 POP {R3}
00000042 4718 BX R3
00000044 ENDP ; 'main'
*** CODE SEGMENT '?PR?delay?T?I2C_Master':
66: void delay (int length)
00000000 ---- Variable 'length' assigned to Register 'R0' ----
68: while (length >0)
00000000 E000 B L_6 ; T=0x00000004
00000002 L_8:
00000002 3801 SUB R0,#0x1
00000004 L_6:
00000004 1C01 MOV R1,R0 ; length
00000006 2900 CMP R1,#0x0 ; length
00000008 DCFB BGT L_8 ; T=0x00000002
70: }
0000000A 4770 BX R14
0000000C ENDP ; 'delay?T'
*** CODE SEGMENT '?PR?IRQ_Handler?A?I2C_Master':
80: void IRQ_Handler() __irq
00000000 E92D000F STMDB R13!,{R0-R3}
83: if(((I2C0MSTA & 0x4) == 0x4) && (i < 8)) // Master Transmit IRQ
00000004 E5100000 LDR R0,=0xFFFF0800
00000008 E5900000 LDR R0,[R0,#0x0]
0000000C E3100004 TST R0,#0x0004
00000010 0A00000A BEQ L_10 ; Targ=0x40
00000014 E5100000 LDR R0,=i ; i
00000018 E5901000 LDR R1,[R0,#0x0] ; i
0000001C E3510008 CMP R1,#0x0008
00000020 AA000006 BGE L_10 ; Targ=0x40
85: i++; // Transmits numbers 1-8
00000024 E5100000 LDR R0,=i ; i
00000028 E2811001 ADD R1,R1,#0x0001
0000002C E5801000 STR R1,[R0,#0x0] ; i
86: I2C0MTX = i;
00000030 E5100000 LDR R0,=i ; i
00000034 E5901000 LDR R1,[R0,#0x0] ; i
00000038 E5100000 LDR R0,=0xFFFF0814
0000003C E5801000 STR R1,[R0,#0x0]
87: }
00000040 L_10:
91: if((I2C0MSTA & 0x8) == 0x8) // Master Recieve IRQ
00000040 E5100000 LDR R0,=0xFFFF0800
00000044 E5900000 LDR R0,[R0,#0x0]
00000048 E3100008 TST R0,#0x0008
0000004C 0A000009 BEQ L_11 ; Targ=0x78
93: dat[i] = I2C0MRX;
00000050 E5100000 LDR R0,=0xFFFF0810
00000054 E5900000 LDR R0,[R0,#0x0]
00000058 E5101000 LDR R1,=i ; i
0000005C E5911000 LDR R1,[R1,#0x0] ; i
00000060 E1A03101 MOV R3,R1,LSL #2
00000064 E5102000 LDR R2,=dat ; dat
00000068 E7820003 STR R0,[R2,+R3]
94: i++;
0000006C E5100000 LDR R0,=i ; i
00000070 E2811001 ADD R1,R1,#0x0001
00000074 E5801000 STR R1,[R0,#0x0] ; i
95: }
00000078 L_11:
96: }
00000078 E8BD000F LDMIA R13!,{R0-R3}
0000007C E25EF004 SUBS R15,R14,#0x0004
00000080 ENDP ; 'IRQ_Handler?A'
ARM COMPILER V2.42, I2C_Master 09/01/06 14:42:27 PAGE 5
Module Information Static
----------------------------------
code size = ------
data size = 24
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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