📄 flash.lst
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ARM COMPILER V2.42, Flash 09/01/06 14:42:49 PAGE 1
ARM COMPILER V2.42, COMPILATION OF MODULE Flash
OBJECT MODULE PLACED IN Flash.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe Flash.c THUMB DEBUG TABS(4)
stmt level source
1 /*********************************************************************
2
3 Author : ADI - Apps www.analog.com/MicroConverter
4
5 Date : Sept. 2005
6
7 File : Flash.c , RAM.c
8
9 Hardware : Applicable to ADuC702x rev H or I silicon
10 Currently targetting ADuC7026.
11
12 Description : This example demonstrate how to place the Interrupt
13 Vector Table in RAM, perform a REMAP, i.e. map RAM to
14 0x00, and wait in a loop for the XIRQ0 button to be
15 pressed, and compliment p4.2. The code to place the
16 vector table in RAM and perform the REMAP is found in
17 the startup.s file
18
19
20 Note : The memory regions in the linker have being changed.
21 The Data region is changed from Start 0x10000 and size
22 0x2000 to Start 0x10040 and size 0x1FC0.
23
24 *********************************************************************/
25
26 #include<ADuC7026.h>
27
28
29 // Main Function
30
31 int main (void)
32 {
33 1 GP4DAT = 0x04040000; // Enable P4.2 as an Output
34 1
35 1 IRQEN = XIRQ0_BIT;
36 1
37 1 while(1){ // Infinite loop
38 2 }
39 1 return(0);
40 1 }
41
42
ARM COMPILER V2.42, Flash 09/01/06 14:42:49 PAGE 2
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC main
*** CODE SEGMENT '?PR?main?Flash':
31: int main (void)
00000000 B500 PUSH {LR}
33: GP4DAT = 0x04040000; // Enable P4.2 as an Output
00000002 4800 LDR R1,=0x4040000
00000004 4800 LDR R0,=0xFFFFF460
00000006 6001 STR R1,[R0,#0x0]
35: IRQEN = XIRQ0_BIT;
00000008 4800 LDR R1,=0x8000
0000000A 4800 LDR R0,=0xFFFF0008
0000000C 6001 STR R1,[R0,#0x0]
38: }
0000000E L_1:
0000000E E7FE B L_1 ; T=0x0000000E
40: }
00000010 BC08 POP {R3}
00000012 4718 BX R3
00000014 ENDP ; 'main'
Module Information Static
----------------------------------
code size = ------
data size = ------
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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