📄 protect.lst
字号:
48: COMCON0 = 0x80; // Setting DLAB
00000026 2180 MOV R1,#0x80
00000028 4800 LDR R0,=0xFFFF070C
0000002A 6001 STR R1,[R0,#0x0]
49: COMDIV0 = 0x88; // updated for rev H
ARM COMPILER V2.42, protect 10/12/07 17:51:27 PAGE 5
0000002C 2188 MOV R1,#0x88
0000002E 4800 LDR R0,=0xFFFF0700
00000030 6001 STR R1,[R0,#0x0]
50: COMDIV1 = 0x00;
00000032 2100 MOV R1,#0x0
00000034 4800 LDR R0,=0xFFFF0704
00000036 6001 STR R1,[R0,#0x0]
51: COMCON0 = 0x07; // Clearing DLAB
00000038 2107 MOV R1,#0x7
0000003A 4800 LDR R0,=0xFFFF070C
0000003C 6001 STR R1,[R0,#0x0]
53: GP4DAT = 0x04000000; // configure P4.2 as output
0000003E 4800 LDR R1,=0x4000000
00000040 4800 LDR R0,=0xFFFFF460
00000042 6001 STR R1,[R0,#0x0]
54: FEEMOD = 0x8; // bit 3 should be set to allow erase/write command
00000044 2108 MOV R1,#0x8
00000046 4800 LDR R0,=0xFFFFF804
00000048 6001 STR R1,[R0,#0x0]
74: erase_page(0xF000); // erase page 120-123
0000004A 4800 LDR R0,=0xF000
0000004C F7FF BL erase_page?T ; T=0x0001 (1)
0000004E FFD8 BL erase_page?T ; T=0x0001 (2)
76: count = 0xA;
00000050 250A MOV R5,#0xA
78: if (ERROR){
00000052 4800 LDR R0,=ERROR ; ERROR
00000054 7800 LDRB R0,[R0,#0x0] ; ERROR
00000056 2800 CMP R0,#0x0
00000058 D005 BEQ L_19 ; T=0x00000066
79: write(0,output,7); // Output Error message
0000005A A900 ADD R1,R13,#0x0
0000005C 2000 MOV R0,#0x0
0000005E 2207 MOV R2,#0x7
00000060 F7FF BL write?T ; T=0x0001 (1)
00000062 FFCE BL write?T ; T=0x0001 (2)
80: }
00000064 E01F B L_28 ; T=0x000000A6
82: for (i=0;i<10;i++){ // Save data
00000066 L_19:
00000066 2400 MOV R4,#0x0
00000068 L_18:
83: save(0xF000+2*i, count);
00000068 1C20 MOV R0,R4 ; i
0000006A 0040 LSL R0,R0,#0x1 ; i
0000006C 4800 LDR R1,=0xF000
0000006E 1840 ADD R0,R1
00000070 1C29 MOV R1,R5 ; count
00000072 0609 LSL R1,R1,#0x18 ; count
00000074 0E09 LSR R1,R1,#0x18
00000076 F7FF BL save?T ; T=0x0001 (1)
00000078 FFC3 BL save?T ; T=0x0001 (2)
84: count --;
0000007A 3D01 SUB R5,#0x1
0000007C 062D LSL R5,R5,#0x18
0000007E 0E2D LSR R5,R5,#0x18
85: }
00000080 3401 ADD R4,#0x1
00000082 1C20 MOV R0,R4 ; i
00000084 280A CMP R0,#0xA ; i
00000086 D3EF BCC L_18 ; T=0x00000068
87: for (i=0;i<10;i++){ // Output Data
00000088 2400 MOV R4,#0x0
0000008A L_23:
88: senddata (load(0xF000+2*i));
0000008A 1C20 MOV R0,R4 ; i
ARM COMPILER V2.42, protect 10/12/07 17:51:27 PAGE 6
0000008C 0040 LSL R0,R0,#0x1 ; i
0000008E 4800 LDR R1,=0xF000
00000090 1840 ADD R0,R1
00000092 F7FF BL load?T ; T=0x0001 (1)
00000094 FFB5 BL load?T ; T=0x0001 (2)
00000096 0400 LSL R0,R0,#0x10 ; load?T
00000098 0C00 LSR R0,R0,#0x10
0000009A F7FF BL senddata?T ; T=0x0001 (1)
0000009C FFB1 BL senddata?T ; T=0x0001 (2)
89: }
0000009E 3401 ADD R4,#0x1
000000A0 1C20 MOV R0,R4 ; i
000000A2 280A CMP R0,#0xA ; i
000000A4 D3F1 BCC L_23 ; T=0x0000008A
92: while (1){
000000A6 L_28:
000000A6 L_27:
93: GP4DAT ^= 0x00040000; // complement P4.2
000000A6 4800 LDR R2,=0x40000
000000A8 4800 LDR R0,=0xFFFFF460
000000AA 6801 LDR R1,[R0,#0x0]
000000AC 4051 EOR R1,R2
000000AE 6001 STR R1,[R0,#0x0]
94: delay(100000);
000000B0 4800 LDR R0,=0x186A0
000000B2 F7FF BL delay?T ; T=0x0001 (1)
000000B4 FFA5 BL delay?T ; T=0x0001 (2)
95: }
000000B6 E7F6 B L_27 ; T=0x000000A6
99: return 0;
000000B8 ; SCOPE-END
100: }
000000B8 B002 ADD R13,#0x8
000000BA BC08 POP {R3}
000000BC 4718 BX R3
000000BE ENDP ; 'main'
*** CODE SEGMENT '?PR?delay?T?protect':
102: void delay (int length) { // delay
00000000 ---- Variable 'length' assigned to Register 'R0' ----
103: while (length >= 0)
00000000 E000 B L_30 ; T=0x00000004
00000002 L_32:
00000002 3801 SUB R0,#0x1
00000004 L_30:
00000004 1C01 MOV R1,R0 ; length
00000006 2900 CMP R1,#0x0 ; length
00000008 DAFB BGE L_32 ; T=0x00000002
105: }
0000000A 4770 BX R14
0000000C ENDP ; 'delay?T'
*** CODE SEGMENT '?PR?protect_page?T?protect':
107: void protect_page(unsigned int addr){
00000000 ---- Variable 'addr' assigned to Register 'R0' ----
108: FEEADR = 0x1234; // Key
00000000 4800 LDR R2,=0x1234
00000002 4800 LDR R1,=0xFFFFF810
00000004 600A STR R2,[R1,#0x0]
109: FEEDAT = 0xA5A5; // Key
00000006 4800 LDR R2,=0xA5A5
00000008 4800 LDR R1,=0xFFFFF80C
0000000A 600A STR R2,[R1,#0x0]
110: FEEPRO = addr;
0000000C 1C01 MOV R1,R0 ; addr
0000000E 4800 LDR R0,=0xFFFFF81C
00000010 6001 STR R1,[R0,#0x0]
111: FEEMOD = 0x48;
ARM COMPILER V2.42, protect 10/12/07 17:51:27 PAGE 7
00000012 2148 MOV R1,#0x48
00000014 4800 LDR R0,=0xFFFFF804
00000016 6001 STR R1,[R0,#0x0]
112: FEECON = 0x0C;
00000018 210C MOV R1,#0xC
0000001A 4800 LDR R0,=0xFFFFF808
0000001C 6001 STR R1,[R0,#0x0]
113: status = FEESTA&0x03;
0000001E 4800 LDR R0,=0xFFFFF800
00000020 6801 LDR R1,[R0,#0x0]
00000022 2003 MOV R0,#0x3
00000024 4001 AND R1,R0
00000026 0609 LSL R1,R1,#0x18
00000028 0E09 LSR R1,R1,#0x18
0000002A 4800 LDR R0,=status ; status
0000002C 7001 STRB R1,[R0,#0x0] ; status
114: while (!(status)) status = FEESTA&0x03;
0000002E E007 B L_34 ; T=0x00000040
00000030 L_36:
00000030 4800 LDR R0,=0xFFFFF800
00000032 6801 LDR R1,[R0,#0x0]
00000034 2003 MOV R0,#0x3
00000036 4001 AND R1,R0
00000038 0609 LSL R1,R1,#0x18
0000003A 0E09 LSR R1,R1,#0x18
0000003C 4800 LDR R0,=status ; status
0000003E 7001 STRB R1,[R0,#0x0] ; status
00000040 L_34:
00000040 4800 LDR R0,=status ; status
00000042 7800 LDRB R0,[R0,#0x0] ; status
00000044 1C01 MOV R1,R0
00000046 2900 CMP R1,#0x0
00000048 D0F2 BEQ L_36 ; T=0x00000030
115: if ((status&0x02)==0x02) ERROR = 1;
0000004A 2102 MOV R1,#0x2
0000004C 4208 TST R0,R1
0000004E D002 BEQ L_38 ; T=0x00000056
00000050 2101 MOV R1,#0x1
00000052 4800 LDR R0,=ERROR ; ERROR
00000054 7001 STRB R1,[R0,#0x0] ; ERROR
00000056 L_38:
117: }
00000056 4770 BX R14
00000058 ENDP ; 'protect_page?T'
*** CODE SEGMENT '?PR?load?T?protect':
120: unsigned short load(unsigned short int addr){
00000000 1C01 MOV R1,R0 ; addr
00000002 ---- Variable 'addr' assigned to Register 'R1' ----
121: FEEADR = addr;
00000002 1C08 MOV R0,R1 ; addr
00000004 0401 LSL R1,R0,#0x10 ; addr
00000006 0C09 LSR R1,R1,#0x10
00000008 4800 LDR R0,=0xFFFFF810
0000000A 6001 STR R1,[R0,#0x0]
122: FEECON = 0x01; // single read command
0000000C 2101 MOV R1,#0x1
0000000E 4800 LDR R0,=0xFFFFF808
00000010 6001 STR R1,[R0,#0x0]
123: status = FEESTA&0x03;
00000012 4800 LDR R0,=0xFFFFF800
00000014 6801 LDR R1,[R0,#0x0]
00000016 2003 MOV R0,#0x3
00000018 4001 AND R1,R0
0000001A 0609 LSL R1,R1,#0x18
0000001C 0E09 LSR R1,R1,#0x18
0000001E 4800 LDR R0,=status ; status
ARM COMPILER V2.42, protect 10/12/07 17:51:27 PAGE 8
00000020 7001 STRB R1,[R0,#0x0] ; status
124: while (!(status)) status = FEESTA&0x03;
00000022 E007 B L_40 ; T=0x00000034
00000024 L_42:
00000024 4800 LDR R0,=0xFFFFF800
00000026 6801 LDR R1,[R0,#0x0]
00000028 2003 MOV R0,#0x3
0000002A 4001 AND R1,R0
0000002C 0609 LSL R1,R1,#0x18
0000002E 0E09 LSR R1,R1,#0x18
00000030 4800 LDR R0,=status ; status
00000032 7001 STRB R1,[R0,#0x0] ; status
00000034 L_40:
00000034 4800 LDR R0,=status ; status
00000036 7800 LDRB R0,[R0,#0x0] ; status
00000038 1C01 MOV R1,R0
0000003A 2900 CMP R1,#0x0
0000003C D0F2 BEQ L_42 ; T=0x00000024
125: if ((status&0x02)==0x02) ERROR = 1;
0000003E 2102 MOV R1,#0x2
00000040 4208 TST R0,R1
00000042 D002 BEQ L_44 ; T=0x0000004A
00000044 2101 MOV R1,#0x1
00000046 4800 LDR R0,=ERROR ; ERROR
00000048 7001 STRB R1,[R0,#0x0] ; ERROR
0000004A L_44:
126: return (FEEDAT);
0000004A 4800 LDR R0,=0xFFFFF80C
0000004C 6800 LDR R0,[R0,#0x0]
127: }
0000004E 4770 BX R14
00000050 ENDP ; 'load?T'
*** CODE SEGMENT '?PR?save?T?protect':
130: void save(unsigned short int addr, unsigned char data){
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -