📄 comp.lst
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ARM COMPILER V2.42, Comp 09/01/06 14:41:25 PAGE 1
ARM COMPILER V2.42, COMPILATION OF MODULE Comp
OBJECT MODULE PLACED IN Comp.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe Comp.c THUMB DEBUG TABS(4)
stmt level source
1 /*********************************************************************
2
3 Author : ADI - Apps www.analog.com/MicroConverter
4
5 Date : Sept. 2005
6
7 File : Comp.c
8
9 Hardware : Applicable to ADuC702x rev H or I silicon
10 Currently targetting ADuC7026.
11
12 Description : When ADC2 > DAC0 an interrupt is triggered.
13 To demonstrate this pull ADC2 high.
14
15 *********************************************************************/
16 #include<ADuC7026.h>
17
18 void delay(int);
19 void IRQ_Handler(void) __irq; // IRQ Function Prototype
20
21
22 unsigned int i;
23
24 int main (void) {
25 1
26 1 GP4DAT = 0x04000000; // P4.2 configured as an output. LED is turned on
27 1 REFCON = 0x01; // internal 2.5V reference. 2.5V on Vref pin
28 1 CMPCON = 0x6E4; // ADC2 > DAC0 => CMPOUT = 1
29 1 // ADC2 < DAC0 => CMPOUT = 0
30 1
31 1 IRQEN = 0x10000; // Enable Comparator
32 1
33 1 DAC0CON = 0x13; // DAC configuration
34 1 // range AVdd/AGND
35 1 // DAC0 is updated with falling edge of core clock
36 1 DAC0DAT = 0x08000000; // set to midscale
37 1
38 1
39 1 while (1)
40 1 {
41 2 }
42 1 }
43
44
45 void delay (int length) {
46 1 while (length >=0) {
47 2 length--;
48 2 }
49 1 }
50
51 /********************************************************************/
52 /* */
53 /* Interrupt Service Rountine */
54 /* */
55 /********************************************************************/
56
57 void IRQ_Handler() __irq
58 {
59 1 if (CMPCON & 0x1) { // falling edge on CMPOUT
ARM COMPILER V2.42, Comp 09/01/06 14:41:25 PAGE 2
60 2 CMPCON = 0x6E5; // clear comparator int bit
61 2 for (i=0; i<=20; i++){
62 3 delay(100000);
63 3 GP4DAT ^= 0x00040000; // Complement P4.2
64 3 }
65 2 }
66 1 if (CMPCON & 0x2) { // rising edge on CMPOUT
67 2 CMPCON = 0x6E6; // clear comparator int bit
68 2 for (i=0; i<=10; i++){
69 3 delay(200000);
70 3 GP4DAT ^= 0x00040000; // Complement P4.2
71 3 }
72 2 }
73 1 return ;
74 1 }
ARM COMPILER V2.42, Comp 09/01/06 14:41:25 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC delay?T
PUBLIC delay?A
PUBLIC IRQ_Handler?A
PUBLIC main
PUBLIC i
*** DATA SEGMENT '?DT0?Comp':
00000000 i:
00000000 DS 4
*** CODE SEGMENT '?PR?main?Comp':
24: int main (void) {
00000000 B500 PUSH {LR}
26: GP4DAT = 0x04000000; // P4.2 configured as an output. LED is turned on
00000002 4800 LDR R1,=0x4000000
00000004 4800 LDR R0,=0xFFFFF460
00000006 6001 STR R1,[R0,#0x0]
27: REFCON = 0x01; // internal 2.5V reference. 2.5V on Vref pin
00000008 2101 MOV R1,#0x1
0000000A 4800 LDR R0,=0xFFFF048C
0000000C 6001 STR R1,[R0,#0x0]
28: CMPCON = 0x6E4; // ADC2 > DAC0 => CMPOUT = 1
0000000E 4800 LDR R1,=0x6E4
00000010 4800 LDR R0,=0xFFFF0444
00000012 6001 STR R1,[R0,#0x0]
31: IRQEN = 0x10000; // Enable Comparator
00000014 4800 LDR R1,=0x10000
00000016 4800 LDR R0,=0xFFFF0008
00000018 6001 STR R1,[R0,#0x0]
33: DAC0CON = 0x13; // DAC configuration
0000001A 2113 MOV R1,#0x13
0000001C 4800 LDR R0,=0xFFFF0600
0000001E 6001 STR R1,[R0,#0x0]
36: DAC0DAT = 0x08000000; // set to midscale
00000020 4800 LDR R1,=0x8000000
00000022 4800 LDR R0,=0xFFFF0604
00000024 6001 STR R1,[R0,#0x0]
41: }
00000026 L_1:
00000026 E7FE B L_1 ; T=0x00000026
42: }
00000028 BC08 POP {R3}
0000002A 4718 BX R3
0000002C ENDP ; 'main'
*** CODE SEGMENT '?PR?delay?T?Comp':
45: void delay (int length) {
00000000 ---- Variable 'length' assigned to Register 'R0' ----
46: while (length >=0) {
00000000 E000 B L_5 ; T=0x00000004
00000002 L_7:
47: length--;
00000002 3801 SUB R0,#0x1
48: }
00000004 L_5:
00000004 1C01 MOV R1,R0 ; length
00000006 2900 CMP R1,#0x0 ; length
00000008 DAFB BGE L_7 ; T=0x00000002
49: }
0000000A 4770 BX R14
ARM COMPILER V2.42, Comp 09/01/06 14:41:25 PAGE 4
0000000C ENDP ; 'delay?T'
*** CODE SEGMENT '?PR?IRQ_Handler?A?Comp':
57: void IRQ_Handler() __irq
00000000 E92D5003 STMDB R13!,{R0-R1,R12,LR}
59: if (CMPCON & 0x1) { // falling edge on CMPOUT
00000004 E5100000 LDR R0,=0xFFFF0444
00000008 E5900000 LDR R0,[R0,#0x0]
0000000C E3100001 TST R0,#0x0001
00000010 0A000013 BEQ L_9 ; Targ=0x64
60: CMPCON = 0x6E5; // clear comparator int bit
00000014 E5101000 LDR R1,=0x6E5
00000018 E5100000 LDR R0,=0xFFFF0444
0000001C E5801000 STR R1,[R0,#0x0]
61: for (i=0; i<=20; i++){
00000020 E3A01000 MOV R1,#0x0
00000024 E5100000 LDR R0,=i ; i
00000028 E5801000 STR R1,[R0,#0x0] ; i
0000002C L_13:
62: delay(100000);
0000002C E5100000 LDR R0,=0x186A0
00000030 EBFFFFF2 BL delay?A ; Targ=0x0
63: GP4DAT ^= 0x00040000; // Complement P4.2
00000034 E5100000 LDR R0,=0xFFFFF460
00000038 E5901000 LDR R1,[R0,#0x0]
0000003C E2211701 EOR R1,R1,#0x40000
00000040 E5801000 STR R1,[R0,#0x0]
64: }
00000044 E5100000 LDR R0,=i ; i
00000048 E5901000 LDR R1,[R0,#0x0] ; i
0000004C E2811001 ADD R1,R1,#0x0001
00000050 E5801000 STR R1,[R0,#0x0] ; i
00000054 E5100000 LDR R0,=i ; i
00000058 E5900000 LDR R0,[R0,#0x0] ; i
0000005C E3500014 CMP R0,#0x0014
00000060 9AFFFFF1 BLS L_13 ; Targ=0x2C
65: }
00000064 L_9:
66: if (CMPCON & 0x2) { // rising edge on CMPOUT
00000064 E5100000 LDR R0,=0xFFFF0444
00000068 E5900000 LDR R0,[R0,#0x0]
0000006C E3100002 TST R0,#0x0002
00000070 0A000013 BEQ L_15 ; Targ=0xC4
67: CMPCON = 0x6E6; // clear comparator int bit
00000074 E5101000 LDR R1,=0x6E6
00000078 E5100000 LDR R0,=0xFFFF0444
0000007C E5801000 STR R1,[R0,#0x0]
68: for (i=0; i<=10; i++){
00000080 E3A01000 MOV R1,#0x0
00000084 E5100000 LDR R0,=i ; i
00000088 E5801000 STR R1,[R0,#0x0] ; i
0000008C L_19:
69: delay(200000);
0000008C E5100000 LDR R0,=0x30D40
00000090 EBFFFFDA BL delay?A ; Targ=0x0
70: GP4DAT ^= 0x00040000; // Complement P4.2
00000094 E5100000 LDR R0,=0xFFFFF460
00000098 E5901000 LDR R1,[R0,#0x0]
0000009C E2211701 EOR R1,R1,#0x40000
000000A0 E5801000 STR R1,[R0,#0x0]
71: }
000000A4 E5100000 LDR R0,=i ; i
000000A8 E5901000 LDR R1,[R0,#0x0] ; i
000000AC E2811001 ADD R1,R1,#0x0001
000000B0 E5801000 STR R1,[R0,#0x0] ; i
000000B4 E5100000 LDR R0,=i ; i
000000B8 E5900000 LDR R0,[R0,#0x0] ; i
ARM COMPILER V2.42, Comp 09/01/06 14:41:25 PAGE 5
000000BC E350000A CMP R0,#0x000A
000000C0 9AFFFFF1 BLS L_19 ; Targ=0x8C
72: }
000000C4 L_15:
74: }
000000C4 E8BD5003 LDMIA R13!,{R0-R1,R12,LR}
000000C8 E25EF004 SUBS R15,R14,#0x0004
000000CC ENDP ; 'IRQ_Handler?A'
Module Information Static
----------------------------------
code size = ------
data size = 4
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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