📄 dacsineclk.lst
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ARM COMPILER V2.32c, DACSineClk 10/09/05 18:34:36 PAGE 1
ARM COMPILER V2.32c, COMPILATION OF MODULE DACSineClk
OBJECT MODULE PLACED IN DACSineClk.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe DACSineClk.c THUMB DEBUG TABS(4)
stmt level source
1 /********************************************************************
2
3 Author : ADI - Apps www.analog.com/MicroConverter
4
5 Date : Sept. 2005
6
7 File : DACsineClk.c
8
9 Hardware : Applicable to ADuC702x rev H or I silicon
10 Currently targetting ADuC7026.
11
12 Description : DAC outputs an intermittent Sine Wave on pin 10 (DAC1).
13 S1.8 must be off
14 To increase the frequency of a Sine Wave reduce
15 T1Delay.
16
17 ********************************************************************/
18
19 #include<ADuC7026.h>
20
21 void IRQ_Handler() __irq;
22
23 // Table is placed in Flash/EE
24 const static unsigned short TableS[64] = {
25 0x07FF, 0x08C8, 0x098E, 0x0A51, 0x0B0F, 0x0BC4, 0x0C71, 0x0D12,
26 0x0DA7, 0x0E2E, 0x0EA5, 0x0F0D, 0x0F63, 0x0FA6, 0x0FD7, 0x0FF5,
27 0x0FFF, 0x0FF5, 0x0FD7, 0x0FA6, 0x0F63, 0x0F0D, 0x0EA5, 0x0E2E,
28 0x0DA7, 0x0D12, 0x0C71, 0x0BC4, 0x0B0F, 0x0A51, 0x098E, 0x08C8,
29 0x07FF, 0x0736, 0x0670, 0x05AD, 0x04EF, 0x043A, 0x038D, 0x02EC,
30 0x0257, 0x01D0, 0x0159, 0x00F1, 0x009B, 0x0058, 0x0027, 0x0009,
31 0x0000, 0x0009, 0x0027, 0x0058, 0x009B, 0x00F1, 0x0159, 0x01D0,
32 0x0257, 0x02EC, 0x038D, 0x043A, 0x04EF, 0x05AD, 0x0670, 0x0736
33 };
34
35 int i = 0;
36
37 int main (void) {
38 1
39 1 unsigned long T1Delay = 0x4000;
40 1
41 1 IRQEN = 0x08;
42 1
43 1 // DAC configuration
44 1 DAC1CON = 0x33; // DAC configuration
45 1 // range AVdd/AGND and Clocked
46 1
47 1 DAC1DAT = 0x08000000; // start from midscale
48 1
49 1 // timer 1 configuration
50 1 T1LD = T1Delay;
51 1 T1CON = 0xC4; // Enable Timer, Periodic and Core CLK / 16
52 1
53 1 while(1)
54 1 {
55 2 }
56 1 return (0);
57 1 }
58
59
ARM COMPILER V2.32c, DACSineClk 10/09/05 18:34:36 PAGE 2
60 void IRQ_Handler() __irq
61 {
62 1 DAC1DAT = (TableS[i] << 16);
63 1 i++;
64 1 i &= 0x03f;
65 1 T1CLRI = 0x01; // Clearing T1 Interupt
66 1 }
ARM COMPILER V2.32c, DACSineClk 10/09/05 18:34:36 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC IRQ_Handler?A
PUBLIC main
PUBLIC i
*** DATA SEGMENT '?CON?DACSineClk':
00000000 TableS:
00000000 BEGIN_INIT
00000000 07FF DW 0x7FF
00000002 08C8 DW 0x8C8
00000004 098E DW 0x98E
00000006 0A51 DW 0xA51
00000008 0B0F DW 0xB0F
0000000A 0BC4 DW 0xBC4
0000000C 0C71 DW 0xC71
0000000E 0D12 DW 0xD12
00000010 0DA7 DW 0xDA7
00000012 0E2E DW 0xE2E
00000014 0EA5 DW 0xEA5
00000016 0F0D DW 0xF0D
00000018 0F63 DW 0xF63
0000001A 0FA6 DW 0xFA6
0000001C 0FD7 DW 0xFD7
0000001E 0FF5 DW 0xFF5
00000020 0FFF DW 0xFFF
00000022 0FF5 DW 0xFF5
00000024 0FD7 DW 0xFD7
00000026 0FA6 DW 0xFA6
00000028 0F63 DW 0xF63
0000002A 0F0D DW 0xF0D
0000002C 0EA5 DW 0xEA5
0000002E 0E2E DW 0xE2E
00000030 0DA7 DW 0xDA7
00000032 0D12 DW 0xD12
00000034 0C71 DW 0xC71
00000036 0BC4 DW 0xBC4
00000038 0B0F DW 0xB0F
0000003A 0A51 DW 0xA51
0000003C 098E DW 0x98E
0000003E 08C8 DW 0x8C8
00000040 07FF DW 0x7FF
00000042 0736 DW 0x736
00000044 0670 DW 0x670
00000046 05AD DW 0x5AD
00000048 04EF DW 0x4EF
0000004A 043A DW 0x43A
0000004C 038D DW 0x38D
0000004E 02EC DW 0x2EC
00000050 0257 DW 0x257
00000052 01D0 DW 0x1D0
00000054 0159 DW 0x159
00000056 00F1 DW 0xF1
00000058 009B DW 0x9B
0000005A 0058 DW 0x58
0000005C 0027 DW 0x27
0000005E 0009 DW 0x9
00000060 0000 DW 0x0
00000062 0009 DW 0x9
00000064 0027 DW 0x27
00000066 0058 DW 0x58
ARM COMPILER V2.32c, DACSineClk 10/09/05 18:34:36 PAGE 4
00000068 009B DW 0x9B
0000006A 00F1 DW 0xF1
0000006C 0159 DW 0x159
0000006E 01D0 DW 0x1D0
00000070 0257 DW 0x257
00000072 02EC DW 0x2EC
00000074 038D DW 0x38D
00000076 043A DW 0x43A
00000078 04EF DW 0x4EF
0000007A 05AD DW 0x5AD
0000007C 0670 DW 0x670
0000007E 0736 DW 0x736
00000080 END_INIT
*** DATA SEGMENT '?DT0?DACSineClk':
00000000 i:
00000000 BEGIN_INIT
00000000 00000000 DD 0x0
00000004 END_INIT
*** CODE SEGMENT '?PR?main?DACSineClk':
37: int main (void) {
00000000 B500 PUSH {LR}
00000002 ; SCOPE-START
39: unsigned long T1Delay = 0x4000;
00000002 4800 LDR R2,=0x4000
00000004 ---- Variable 'T1Delay' assigned to Register 'R2' ----
41: IRQEN = 0x08;
00000004 2108 MOV R1,#0x8
00000006 4800 LDR R0,=0xFFFF0008
00000008 6001 STR R1,[R0,#0x0]
44: DAC1CON = 0x33; // DAC configuration
0000000A 2133 MOV R1,#0x33
0000000C 4800 LDR R0,=0xFFFF0608
0000000E 6001 STR R1,[R0,#0x0]
47: DAC1DAT = 0x08000000; // start from midscale
00000010 4800 LDR R1,=0x8000000
00000012 4800 LDR R0,=0xFFFF060C
00000014 6001 STR R1,[R0,#0x0]
50: T1LD = T1Delay;
00000016 1C11 MOV R1,R2 ; T1Delay
00000018 4800 LDR R0,=0xFFFF0320
0000001A 6001 STR R1,[R0,#0x0]
51: T1CON = 0xC4; // Enable Timer, Periodic and Core CLK / 16
0000001C 21C4 MOV R1,#0xC4
0000001E 4800 LDR R0,=0xFFFF0328
00000020 6001 STR R1,[R0,#0x0]
55: }
00000022 L_1:
00000022 E7FE B L_1 ; T=0x00000022
56: return (0);
00000024 ; SCOPE-END
57: }
00000024 BC08 POP {R3}
00000026 4718 BX R3
00000028 ENDP ; 'main'
*** CODE SEGMENT '?PR?IRQ_Handler?A?DACSineClk':
60: void IRQ_Handler() __irq
00000000 E92D0007 STMDB R13!,{R0-R2}
62: DAC1DAT = (TableS[i] << 16);
00000004 E5100000 LDR R0,=i ; i
00000008 E5901000 LDR R1,[R0,#0x0] ; i
0000000C E1A02081 MOV R2,R1,LSL #1
00000010 E5100000 LDR R0,=TableS ; TableS
00000014 E19000B2 LDRH R0,[R0,R2]
00000018 E1A02000 MOV R2,R0
0000001C E1A02802 MOV R2,R2,LSL #16
ARM COMPILER V2.32c, DACSineClk 10/09/05 18:34:36 PAGE 5
00000020 E5100000 LDR R0,=0xFFFF060C
00000024 E5802000 STR R2,[R0,#0x0]
63: i++;
00000028 E5100000 LDR R0,=i ; i
0000002C E2811001 ADD R1,R1,#0x0001
00000030 E5801000 STR R1,[R0,#0x0] ; i
64: i &= 0x03f;
00000034 E5100000 LDR R0,=i ; i
00000038 E5901000 LDR R1,[R0,#0x0] ; i
0000003C E201103F AND R1,R1,#0x003F
00000040 E5100000 LDR R0,=i ; i
00000044 E5801000 STR R1,[R0,#0x0] ; i
65: T1CLRI = 0x01; // Clearing T1 Interupt
00000048 E3A01001 MOV R1,#0x1
0000004C E5100000 LDR R0,=0xFFFF032C
00000050 E5801000 STR R1,[R0,#0x0]
00000054 E8BD0007 LDMIA R13!,{R0-R2}
00000058 E25EF004 SUBS R15,R14,#0x0004
0000005C ENDP ; 'IRQ_Handler?A'
Module Information Static
----------------------------------
code size = ------
data size = 4
const size = 128
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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