📄 dacsine.lst
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ARM COMPILER V2.53, DACsine 10/12/07 17:36:19 PAGE 1
ARM COMPILER V2.53, COMPILATION OF MODULE DACsine
OBJECT MODULE PLACED IN DACsine.OBJ
COMPILER INVOKED BY: d:\Keil\ARM\BIN\CA.exe DACsine.c THUMB DEBUG TABS(4)
stmt level source
1 /********************************************************************
2
3 Author : ADI - Apps www.analog.com/MicroConverter
4
5 Date : Sept. 2005
6
7 File : DACsine.c
8
9 Hardware : Applicable to ADuC702x rev H or I silicon
10 Currently targetting ADuC7026.
11
12 Description : DAC outputs a sine wave on pin 10 (DAC1). S1.8 must be off
13 DAC is updated with core clock frequency 45MHz.
14
15 ********************************************************************/
16
17 #include<ADuC7026.h>
18
19 int main (void) {
20 1 // Table is placed in Flash/EE
21 1 const static unsigned short TableS[64] = {
22 1 0x07FF, 0x08C8, 0x098E, 0x0A51, 0x0B0F, 0x0BC4, 0x0C71, 0x0D12,
23 1 0x0DA7, 0x0E2E, 0x0EA5, 0x0F0D, 0x0F63, 0x0FA6, 0x0FD7, 0x0FF5,
24 1 0x0FFF, 0x0FF5, 0x0FD7, 0x0FA6, 0x0F63, 0x0F0D, 0x0EA5, 0x0E2E,
25 1 0x0DA7, 0x0D12, 0x0C71, 0x0BC4, 0x0B0F, 0x0A51, 0x098E, 0x08C8,
26 1 0x07FF, 0x0736, 0x0670, 0x05AD, 0x04EF, 0x043A, 0x038D, 0x02EC,
27 1 0x0257, 0x01D0, 0x0159, 0x00F1, 0x009B, 0x0058, 0x0027, 0x0009,
28 1 0x0000, 0x0009, 0x0027, 0x0058, 0x009B, 0x00F1, 0x0159, 0x01D0,
29 1 0x0257, 0x02EC, 0x038D, 0x043A, 0x04EF, 0x05AD, 0x0670, 0x0736
30 1 };
31 1 int i = 0;
32 1
33 1 // DAC configuration
34 1 DAC1CON = 0x13; // DAC configuration
35 1 // range AVdd/AGND
36 1 // DAC1 is updated with falling edge of core clock
37 1 DAC1DAT = 0x08000000; // start from midscale
38 1
39 1 while(1){
40 2 DAC1DAT = (TableS[i] << 16);
41 2 i++;
42 2 i &= 0x03f;
43 2 }
44 1 return (0);
45 1 }
ARM COMPILER V2.53, DACsine 10/12/07 17:36:19 PAGE 2
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC main
*** DATA SEGMENT '?CON?DACsine':
00000000 TableS:
00000000 BEGIN_INIT
00000000 07FF DW 0x7FF
00000002 08C8 DW 0x8C8
00000004 098E DW 0x98E
00000006 0A51 DW 0xA51
00000008 0B0F DW 0xB0F
0000000A 0BC4 DW 0xBC4
0000000C 0C71 DW 0xC71
0000000E 0D12 DW 0xD12
00000010 0DA7 DW 0xDA7
00000012 0E2E DW 0xE2E
00000014 0EA5 DW 0xEA5
00000016 0F0D DW 0xF0D
00000018 0F63 DW 0xF63
0000001A 0FA6 DW 0xFA6
0000001C 0FD7 DW 0xFD7
0000001E 0FF5 DW 0xFF5
00000020 0FFF DW 0xFFF
00000022 0FF5 DW 0xFF5
00000024 0FD7 DW 0xFD7
00000026 0FA6 DW 0xFA6
00000028 0F63 DW 0xF63
0000002A 0F0D DW 0xF0D
0000002C 0EA5 DW 0xEA5
0000002E 0E2E DW 0xE2E
00000030 0DA7 DW 0xDA7
00000032 0D12 DW 0xD12
00000034 0C71 DW 0xC71
00000036 0BC4 DW 0xBC4
00000038 0B0F DW 0xB0F
0000003A 0A51 DW 0xA51
0000003C 098E DW 0x98E
0000003E 08C8 DW 0x8C8
00000040 07FF DW 0x7FF
00000042 0736 DW 0x736
00000044 0670 DW 0x670
00000046 05AD DW 0x5AD
00000048 04EF DW 0x4EF
0000004A 043A DW 0x43A
0000004C 038D DW 0x38D
0000004E 02EC DW 0x2EC
00000050 0257 DW 0x257
00000052 01D0 DW 0x1D0
00000054 0159 DW 0x159
00000056 00F1 DW 0xF1
00000058 009B DW 0x9B
0000005A 0058 DW 0x58
0000005C 0027 DW 0x27
0000005E 0009 DW 0x9
00000060 0000 DW 0x0
00000062 0009 DW 0x9
00000064 0027 DW 0x27
00000066 0058 DW 0x58
00000068 009B DW 0x9B
0000006A 00F1 DW 0xF1
ARM COMPILER V2.53, DACsine 10/12/07 17:36:19 PAGE 3
0000006C 0159 DW 0x159
0000006E 01D0 DW 0x1D0
00000070 0257 DW 0x257
00000072 02EC DW 0x2EC
00000074 038D DW 0x38D
00000076 043A DW 0x43A
00000078 04EF DW 0x4EF
0000007A 05AD DW 0x5AD
0000007C 0670 DW 0x670
0000007E 0736 DW 0x736
00000080 END_INIT
*** CODE SEGMENT '?PR?main?DACsine':
19: int main (void) {
00000000 B500 PUSH {LR}
00000002 ; SCOPE-START
31: int i = 0;
00000002 2000 MOV R0,#0x0
00000004 ---- Variable 'i' assigned to Register 'R0' ----
34: DAC1CON = 0x13; // DAC configuration
00000004 2213 MOV R2,#0x13
00000006 4800 LDR R1,=0xFFFF0608
00000008 600A STR R2,[R1,#0x0]
37: DAC1DAT = 0x08000000; // start from midscale
0000000A 4800 LDR R2,=0x8000000
0000000C 4800 LDR R1,=0xFFFF060C
0000000E 600A STR R2,[R1,#0x0]
39: while(1){
00000010 L_3:
40: DAC1DAT = (TableS[i] << 16);
00000010 1C02 MOV R2,R0 ; i
00000012 0052 LSL R2,R2,#0x1 ; i
00000014 4800 LDR R1,=TableS ; TableS
00000016 5A89 LDRH R1,[R1,R2]
00000018 1C0A MOV R2,R1
0000001A 0412 LSL R2,R2,#0x10
0000001C 4800 LDR R1,=0xFFFF060C
0000001E 600A STR R2,[R1,#0x0]
41: i++;
00000020 3001 ADD R0,#0x1
42: i &= 0x03f;
00000022 213F MOV R1,#0x3F
00000024 4008 AND R0,R1
43: }
00000026 E7F3 B L_3 ; T=0x00000010
44: return (0);
00000028 ; SCOPE-END
45: }
00000028 BC08 POP {R3}
0000002A 4718 BX R3
0000002C ENDP ; 'main'
Module Information Static
----------------------------------
code size = ------
data size = ------
const size = 128
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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