plldemo.html

对一般的PLL及APLL,定点PLL进行了MATLAB SIMULINK仿真

         <div>
            <ul>
               <li>Simulink can display the datatype in the block diagram</li>
               <li>The same blocks that operate on floating-point data also operate on fixed-point data. Therefor it's easy to switch.</li>
               <li>Simulink can log the range of the model's signals, together with overflows (if any).</li>
               <li>Simulink can suggest and apply fraction lengths, based on the ranges of a reference simulation.</li>
            </ul>
         </div>
         <p>We'll use the all digital PLL to show how to convert a floating-point Simulink model to fixed-point, using the capabilities
            mentioned above.
         </p>
         <p>First, turn on data-type labeling to show the data-types of all the signals in the model: Format menu -&gt; Port/Signal Displays
            -&gt; Port Data Types.
         </p>
         <p>All label read "double" which is a 8 byte floating point data type.</p>
         <p>To convert the model, we'll change the datatype of the NCO (we're actually changing the data type of the entries in the look-up
            table). Open the NCO subsystem and the NCO block's parameter dialog window. Select the second tab to change the block's data
            types.
         </p>
         <p>Set the output data type to Binary point scaling with a Word length of 16 bits and a fraction length of 14 bits.</p>
         <p>Use a data-type conversion block to set the datatype of the reference signal to "Inherit via back propagation".</p>
         <p>Update the diagram. Note that the output of the NCO and the Data type conversion block have changed to sfix16_n14. This data
            type has a range of [-2 2&gt;.
         </p>
         <p>To change the output of the Stateflow block, open the Model Explorer from Stateflow (View menu -&gt; Model Explorer). Next, select
            the s data object in the middle pane, and change it's data type to a 16 bit signed fixed-point number with 14 bits scaling.
         </p>
         <p>Update the diagram, note that the complete model is now fixed-point. Note that we didn't have to make any changes to the algorithm
            itself, or replace any of the blocks in the model.
         </p>
         <p>Running the model shows that the PLL doesn't behave correctly.</p>
         <h2>Optimizing fixed-point data types<a name="27"></a></h2>
         <p>To solve the problem, let's use the fixed-point tooling available in Simulink fixed-point.</p>
         <p><img vspace="5" hspace="5" src="fixpttool.jpg"> </p>
         <p>1. To verify that fixed-point data types indeed are the cause for the incorrect behavior, run a reference simulation with
            Data type override set to "True doubles". Note that the data types in the model changed to "double" again, and that the PLL
            behaves again correctly!
         </p>
         <p>2. Run the reference simulation again, but now with Logging mode set to Minimum, maximums and overflows. Note the logging
            of the ranges (no overflows due to floating-point data types)
         </p>
         <p>3. Run an active simulation again, but with Data type override set to "Use local settings". Note the overflows in the Loop
            Filter block (Accumulator and Product output).
         </p>
         <p>4. Use the autoscaling capabilities of the Fixed-Point Tool to optimize the fraction length of the filter's internal variables.</p>
         <div>
            <ul>
               <li>Open the Fixed-point tab of the Loop filter block's parameter dialog window.</li>
               <li>Change the Rounding Mode to Nearest</li>
               <li>Change the data type mode of all the internal variables to Binary point scaling. Use a 32 bit word length for the Product
                  output and Accumulator and a 16 bit word length for the State and Ouptut.
               </li>
               <li>In the Fixed-Point Tool select Auto-scaling using Reference and set a 10 Percent safety margin Propose and accept the new
                  fraction lengths using the two buttons at the bottom of the Dialog View of the Fixed-Point Tool
               </li>
            </ul>
         </div><pre class="codeoutput">Warning: Parameter precision loss occurred for ''Numerator coefficients''. The parameter's value cannot be represented exactly using the run-time data type. A small quantization error has occurred. You can control this diagnostic on the Diagnostics pane of the Configuration Parameters dialog. This originated from 'dpll_fixpt/Loop Filter'.
Warning: Parameter precision loss occurred for ''Denominator coefficients''. The parameter's value cannot be represented exactly using the run-time data type. A small quantization error has occurred. You can control this diagnostic on the Diagnostics pane of the Configuration Parameters dialog. This originated from 'dpll_fixpt/Loop Filter'.
Warning: Parameter precision loss occurred for ''Numerator coefficients''. The parameter's value cannot be represented exactly using the run-time data type. A small quantization error has occurred. You can control this diagnostic on the Diagnostics pane of the Configuration Parameters dialog. This originated from 'dpll_fixpt/Loop Filter'.
Warning: Parameter precision loss occurred for ''Denominator coefficients''. The parameter's value cannot be represented exactly using the run-time data type. A small quantization error has occurred. You can control this diagnostic on the Diagnostics pane of the Configuration Parameters dialog. This originated from 'dpll_fixpt/Loop Filter'.
Warning: Overflow occurred. This originated from 'dpll_fixpt/NCO/NCO'.
</pre><img vspace="5" hspace="5" src="plldemo_10.png"> <p>Run the simulation again to see that the overflows have dissapeared and that the fixed-point PLL runs as expected!</p><img vspace="5" hspace="5" src="plldemo_11.png"> <p>Note that the PLL locks to the 1.1 MHz input frequency after about 10 mu.</p>
         <h2>Software and Hardware code generation<a name="33"></a></h2>
         <p>This concludes the demo. A next step would be to generate VHDL, Verilog or ANSI C code from the model.</p>
         <h2>Toolboxes and blocksets needed for this demo<a name="34"></a></h2>
         <div>
            <ul>
               <li><b>Linear PLL</b> (<tt>linearpll.mdl</tt>): MATLAB, Simulink, Signal Processing Toolbox, Signal Processing Blockset, Communications Toolbox, Communications Blockset.
               </li>
               <li><b>Charge Pump PLL</b> (<tt>cppll.mdl</tt>): MATLAB, Simulink, Signal Processing Toolbox, Signal Processing Blockset, Communications Toolbox, Communications Blockset,
                  Stateflow
               </li>
               <li><b>PLL with circuit model</b> (<tt>powerpll.mdl</tt>): MATLAB, Simulink, Signal Processing Toolbox, Signal Processing Blockset, Communications Toolbox, Communications Blockset,
                  SimPowerSystems
               </li>
               <li><b>All Digital PLL</b>: MATLAB, Simulink, Signal Processing Toolbox, Signal Processing Blockset, Stateflow.
               </li>
               <li><b>Fixed-Point PLL</b>: MATLAB, Simulink, Signal Processing Toolbox, Signal Processing Blockset, Stateflow, Fixed-Point Toolbox, Simulink Fixed-Point.
               </li>
            </ul>
         </div>
         <p class="footer"><br>
            Published with MATLAB&reg; 7.4<br></p>
      </div>
      <!--
##### SOURCE BEGIN #####
%% Demo: Phase Locked Loop
% This demo shows the executable specifications and design with simulation
% capabilities of Simulink. It highlights:
%  
% 1. Creating conceptual models of signal processing systems and running
% simulations
%
% 2. Adding finite state machines to the design
%
% 3. Creating models of physical components (e.g. circuitery)
%
% 4. Using discrete-time signal to create mixed-signal models
%
% 5. Converting digital models to fixed-point
%
% 6. Optional: (not implemented yet) generating C and/or HDL

%% What is a Phase-Locked Loop?
% A phase-locked loop (PLL) is a closed-loop feedback control system that
% generates and outputs a signal in relation to the frequency and phase of
% an input ("reference") signal. A phase-locked loop circuit responds to
% both the frequency and the phase of the input signals, automatically
% raising or lowering the frequency of a controlled oscillator until it is
% matched to the reference in both frequency and phase.
% 
% This type of mechanism is widely used in radio, telecommunications,
% computers and other electronic applications where it is desired to
% stabilize a generated signal or to detect signals in the presence of
% noise. Since an integrated circuit can hold a complete phase-locked loop
% building block, the technique is widely used in modern electronic
% devices, with signal frequencies from a fraction of a cycle per second up
% to many gigahertz.  (Source: wikipedia.org.)


%% A linear Phase Locked Loop in Simulink
% The first step of the demo shows how to model and simulate a linear PLL
% that can track a 1 MHz reference signal.
%
% A classic or linear PLL uses a mixer as a phase detector. This yields a
% DC component that is proportional (but not linear) with the phase
% difference and a component at a frequency that is twice the input
% frequency. A loop filter is used to get rid of the second component. The
% output of the loop filter is fed into a VCO that increases the freqeuncy
% if there is a positive phase difference and that decreases the frequency
% if there is a negative phase difference.
%
% Start with the basic components of a PLL: a Multiply block (Math
% Library), an Analog Filter Design block (Filter Design library in the
% Signal Processing Blockset) and a Voltage Controlled Oscillator
% (Communications Blockset, Components sublibrary in the Synchronization
% library).
%
% Double click on the blocks to show how to set the parameters for each
% block:
%
% The Analog Filter Design block;
%    Design method: butterworth,
%    Filter type: Lowpass,
%    Filter order: 5,
%    Passband edge frequency: 1e6*2*pi.
%
% The VCO block;
%    Quiescent frequency: 1e6,
%    Input sensitivity: 1e5,
%    Initial phase: 0.

open_system('linearpll'); set_param(bdroot,'SimulationCommand', 'update')
sim(bdroot);

%%
% In order to simulate the system, we need a test input and vizualiation.
% To achieve this, add a Sine wave block (Simulink Sources Library) and a
% Scope block (Simulink Sinks library) to the model. Set the parameters of
% the Sine wave to:
%
% Sine Wave block;
%    Frequency: 2*pi*1e6,
%    All other parameters: default.
%
% Add another axes to the Scope block, and connect the two inputs to the
% outputs of the Sine Wave block and the VCO block. Change the simulation
% time to 50 periods (50e-6). Connect a second Scope block to the output of
% the Butterworth filter. Label the block appropriately. Run the
% simulation!

figure('Color', 'White');
plot(log_linearpll.time*1e6, [log_linearpll.signals.values]);
 grid; axis([0 10 -1 1]);legend('Reference', 'PLL');
xlabel('Time (\mus)'); set(gcf,'Position', [360   502   560   267]);
ylabel('Voltage (V)');

%%
% To assess the quality of the PLL we are going to look at the spectrum of
% the generated signal. Add a Spectrum Scope block from the Signal
% Processing Sinks library and change it's parameters:
%
% Spectrum Scope parameters;
%    Buffer input: on,
%    Buffer size: 512,
%    Buffer overlap: 256,
%    Window type: Kaiser,
%    Beta: 5,
%    Specify FFT length: off,
%    Number of Spectral averages: 1.

pwelch(log_linearpll.signals(2).values,kaiser(1024,5),512,[],1e8)

%%
% To test how robust the PLL behaves to phase and frequency differences we
% can change the Frequency and Phase offset parameters of the Sine. For
% example, the PLL locks at frequencies up to about 1.05 MHz, but it fails
% to lock at 1.1 MHz. Also, for frequencies other then 1 MHz, the generated
% signal will have a phase offset with respect to the carrier (the reason
% being that the butterworth filter doesn't have a pole at zero (no pure
% integrator). Also note the ripple on the control signal, which is due to
% the second harmonics of the multiplication.

%% A charge-pump PLL with digital Phase-Frequency Detector in Simulink
% Better results can be achieved with a charge pump and a loop filter. The
% charge pump, "pumps" current into a 2nd order loop filter. The branch
% voltage of the loop filter is used as input to the VCO. A digital phase
% frequency detector (PFD) determines whether a positive or negative
% current is pumped into the filter. Phase lead corresponds to a negative
% frequency (output and thus VCO frequency decreases) whereas phase lag
% corresponds to a positive current.
% 
% The PFD is typically a finite state machine that reponds to
% zero-crossings of the input signals. If the reference signal has a
% positive edge first a switch is turned on that pumps a positive
% current into the loop filter, until a positive edge of the VCO signal is
% detected (phase lag).

%%
% We'll start by creating a behavioral model of the PLL. To model the PFD
% we use a Stateflow machine. Create the chart according to the diagram
% below:
%%
% <<pfd.jpg>>
%
%%
% Update the diagram and create input events (Rising Edge) for Ref and Var
% and an output variable for s. To be able to feed the reference signal and
% VCO signal to the Chart, use a Mux block (Simulink routing library)
%
% Implement the charge pump with a Gain block. Set the gain parameter to
% 260e-6 (Ampere). A behavioral model for the loop filter can be created
% with a simple Transfer Fcn block. To set the parameters of this block, we
% need to find the transfer function for the loop filter. Applying the
% Laplace transform to the differential equations yields:
%