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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN"><html xmlns:mwsh="http://www.mathworks.com/namespace/mcode/v1/syntaxhighlight.dtd"> <head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> <!--This HTML is auto-generated from an M-file.To make changes, update the M-file and republish this document. --> <title>Demo: Phase Locked Loop</title> <meta name="generator" content="MATLAB 7.4"> <meta name="date" content="2007-05-04"> <meta name="m-file" content="plldemo"><style>body { background-color: white; margin:10px;}h1 { color: #990000; font-size: x-large;}h2 { color: #990000; font-size: medium;}/* Make the text shrink to fit narrow windows, but not stretch too far in wide windows. */ p,h1,h2,div.content div { max-width: 600px; /* Hack for IE6 */ width: auto !important; width: 600px;}pre.codeinput { background: #EEEEEE; padding: 10px;}@media print { pre.codeinput {word-wrap:break-word; width:100%;}} span.keyword {color: #0000FF}span.comment {color: #228B22}span.string {color: #A020F0}span.untermstring {color: #B20000}span.syscmd {color: #B28C00}pre.codeoutput { color: #666666; padding: 10px;}pre.error { color: red;}p.footer { text-align: right; font-size: xx-small; font-weight: lighter; font-style: italic; color: gray;} </style></head> <body> <div class="content"> <h1>Demo: Phase Locked Loop</h1> <introduction> <p>This demo shows the executable specifications and design with simulation capabilities of Simulink. It highlights:</p> <p>1. Creating conceptual models of signal processing systems and running simulations</p> <p>2. Adding finite state machines to the design</p> <p>3. Creating models of physical components (e.g. circuitery)</p> <p>4. Using discrete-time signal to create mixed-signal models</p> <p>5. Converting digital models to fixed-point</p> <p>6. Optional: (not implemented yet) generating C and/or HDL</p> </introduction> <h2>Contents</h2> <div> <ul> <li><a href="#1">What is a Phase-Locked Loop?</a></li> <li><a href="#2">A linear Phase Locked Loop in Simulink</a></li> <li><a href="#6">A charge-pump PLL with digital Phase-Frequency Detector in Simulink</a></li> <li><a href="#11">An implementation for the PFD, Charge Pump and Loop filter</a></li> <li><a href="#14">An all digital PLL in Simulink</a></li> <li><a href="#22">Converting the digital PLl to fixed-point.</a></li> <li><a href="#27">Optimizing fixed-point data types</a></li> <li><a href="#33">Software and Hardware code generation</a></li> <li><a href="#34">Toolboxes and blocksets needed for this demo</a></li> </ul> </div> <h2>What is a Phase-Locked Loop?<a name="1"></a></h2> <p>A phase-locked loop (PLL) is a closed-loop feedback control system that generates and outputs a signal in relation to the frequency and phase of an input ("reference") signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. </p> <p>This type of mechanism is widely used in radio, telecommunications, computers and other electronic applications where it is desired to stabilize a generated signal or to detect signals in the presence of noise. Since an integrated circuit can hold a complete phase-locked loop building block, the technique is widely used in modern electronic devices, with signal frequencies from a fraction of a cycle per second up to many gigahertz. (Source: wikipedia.org.) </p> <h2>A linear Phase Locked Loop in Simulink<a name="2"></a></h2> <p>The first step of the demo shows how to model and simulate a linear PLL that can track a 1 MHz reference signal.</p> <p>A classic or linear PLL uses a mixer as a phase detector. This yields a DC component that is proportional (but not linear) with the phase difference and a component at a frequency that is twice the input frequency. A loop filter is used to get rid of the second component. The output of the loop filter is fed into a VCO that increases the freqeuncy if there is a positive phase difference and that decreases the frequency if there is a negative phase difference. </p> <p>Start with the basic components of a PLL: a Multiply block (Math Library), an Analog Filter Design block (Filter Design library in the Signal Processing Blockset) and a Voltage Controlled Oscillator (Communications Blockset, Components sublibrary in the Synchronization library). </p> <p>Double click on the blocks to show how to set the parameters for each block:</p> <p>The Analog Filter Design block; Design method: butterworth, Filter type: Lowpass, Filter order: 5, Passband edge frequency: 1e6*2*pi. </p> <p>The VCO block; Quiescent frequency: 1e6, Input sensitivity: 1e5, Initial phase: 0.</p><img vspace="5" hspace="5" src="plldemo_01.png"> <p>In order to simulate the system, we need a test input and vizualiation. To achieve this, add a Sine wave block (Simulink Sources Library) and a Scope block (Simulink Sinks library) to the model. Set the parameters of the Sine wave to: </p> <p>Sine Wave block; Frequency: 2*pi*1e6, All other parameters: default.</p> <p>Add another axes to the Scope block, and connect the two inputs to the outputs of the Sine Wave block and the VCO block. Change the simulation time to 50 periods (50e-6). Connect a second Scope block to the output of the Butterworth filter. Label the block appropriately. Run the simulation! </p><img vspace="5" hspace="5" src="plldemo_02.png"> <p>To assess the quality of the PLL we are going to look at the spectrum of the generated signal. Add a Spectrum Scope block from the Signal Processing Sinks library and change it's parameters: </p> <p>Spectrum Scope parameters; Buffer input: on, Buffer size: 512, Buffer overlap: 256, Window type: Kaiser, Beta: 5, Specify FFT length: off, Number of Spectral averages: 1. </p><img vspace="5" hspace="5" src="plldemo_03.png"> <p>To test how robust the PLL behaves to phase and frequency differences we can change the Frequency and Phase offset parameters of the Sine. For example, the PLL locks at frequencies up to about 1.05 MHz, but it fails to lock at 1.1 MHz. Also, for frequencies other then 1 MHz, the generated signal will have a phase offset with respect to the carrier (the reason being that the butterworth filter doesn't have a pole at zero (no pure integrator). Also note the ripple on the control signal, which is due to the second harmonics of the multiplication. </p> <h2>A charge-pump PLL with digital Phase-Frequency Detector in Simulink<a name="6"></a></h2> <p>Better results can be achieved with a charge pump and a loop filter. The charge pump, "pumps" current into a 2nd order loop filter. The branch voltage of the loop filter is used as input to the VCO. A digital phase frequency detector (PFD) determines whether a positive or negative current is pumped into the filter. Phase lead corresponds to a negative frequency (output and thus VCO frequency decreases) whereas phase lag corresponds to a positive current. </p> <p>The PFD is typically a finite state machine that reponds to zero-crossings of the input signals. If the reference signal has a positive edge first a switch is turned on that pumps a positive current into the loop filter, until a positive edge of the VCO signal is detected (phase lag). </p> <p>We'll start by creating a behavioral model of the PLL. To model the PFD we use a Stateflow machine. Create the chart according to the diagram below: </p> <p><img vspace="5" hspace="5" src="pfd.jpg"> </p> <p>Update the diagram and create input events (Rising Edge) for Ref and Var and an output variable for s. To be able to feed the reference signal and VCO signal to the Chart, use a Mux block (Simulink routing library) </p> <p>Implement the charge pump with a Gain block. Set the gain parameter to 260e-6 (Ampere). A behavioral model for the loop filter can be created with a simple Transfer Fcn block. To set the parameters of this block, we need to find the transfer function for the loop filter. Applying the Laplace transform to the differential equations yields: </p> <p><img vspace="5" hspace="5" src="plldemo_eq79689.png"> </p> <p>Set the Numerator coefficient of the Transfer Fcn block to [R1*C1, 1], and set the Denominator coefficient to [C1*C2*R1, (C1+C2), 0]. Next, adjust the loop gain by changing the Input Sensitivity of the VCO to 3e5. Change the Initial phase to -pi/2. </p> <p>Assign values to variables <tt>C1</tt>, <tt>C2</tt> and <tt>R1</tt> in the MATLAB workspace: </p><pre>C2 = 17e-12;C1 = 82e-12;R1 = 23e3;</pre><p>Run the simulation with the Stateflow Chart open to see the animation.</p> <p>Experiment with the Phase offset and Frequency of the Sine Wave block to test the PLL.</p><img vspace="5" hspace="5" src="plldemo_04.png"> <h2>An implementation for the PFD, Charge Pump and Loop filter<a name="11"></a></h2> <p>In the previous model we used behaviorable models for the PFD (state chart), charge pump (Gain) and loop filter (transfer function). Simulink also has the capabilities to simulate an physical implementation for these three components. </p> <p>Open the model <tt>powerpll</tt> to see an example. </p><img vspace="5" hspace="5" src="plldemo_05.png"> <img vspace="5" hspace="5" src="plldemo_06.png"> <img vspace="5" hspace="5" src="plldemo_07.png"> <p>In this example the phase frequency detector is implemented by two flipflops and a NAND gate. The charge pump and loop filter are implemented using blocks from the SimPowerSystem blockset. This extension to Simulink makes it possible to draw electrical circuits directly in Simulink. This eliminates the neccesity to derive differential equations and transfer functions and facilitates experimenting with different network topologies. </p> <p>Run the simulation to validate the correct behavior of the PLL.</p> <h2>An all digital PLL in Simulink<a name="14"></a></h2> <p>PLLs are used more and more in the digital domain, this means that apart for the Phase Frequency Detector, also the loop filter and VCO need to be to be converted to discrete-time systems. The loop filter can be converted from Laplace to the z-domain using an appropriate transformation (e.g. Zero-Order Hold, Bilinear etc). The VCO (Voltage Controlled Oscillator) need to be replaced by an NCO (Numerically Controlled Oscilaator). </p> <p>Open the model <tt>dpll</tt> to see an example. </p><img vspace="5" hspace="5" src="plldemo_08.png"> <p>The digital filter has been implemented using a Digital Filter block from the Signal Processing blockset's Filter Design library. The filter coefficients can be reproduced using the following code: </p><pre>G = tf([0 R1*C1, 1],[C1*C2*R1, (C1+C2), 0])</pre><pre class="codeoutput"> Transfer function: 1.886e-006 s + 1---------------------------3.206e-017 s^2 + 9.9e-011 s </pre><p><tt>Gd = c2d(G,1e-8)</tt></p><pre class="codeoutput"> Transfer function: 580.8 z - 577.7---------------------z^2 - 1.97 z + 0.9696 Sampling time: 1e-008</pre><p><tt>a = Gd.den{1}</tt></p><pre class="codeoutput">a = 1.0000 -1.9696 0.9696</pre><p><tt>b= Gd.num{1}/Gd.num{1}(2)</tt></p><pre class="codeoutput">b = 0 1.0000 -0.9947</pre><p>The VCO has been replaced by a subsystem containing a block that converts the output of the filter to an incremental value that loops through a look-up table of the NCO block. The constant increment value that is added corresponds to a frequency of approximately 1MHz. The unit delay block is used as a register that makes this system realizable in software (in Simulink it breaks the algebraic loop). </p><img vspace="5" hspace="5" src="plldemo_09.png"> <p>This digital PLL can be automatically converted to floating-point ANSI C code using Real-Time Workshop.</p> <h2>Converting the digital PLl to fixed-point.<a name="22"></a></h2> <p>Many signal processing systems are implemented as hand-held devices (e.g. GPS, Mobile phones, multi-media) and need to be cost-effictive. Therefor, it is often necessary to convert the system's data-types to fixed-point in order to implement the algorithm on either a fixed-point DSP, an FPGA or an ASIC (Application Specific Integrated Circuit). </p> <p>Fixed-pont data types however introduce a number of serious challenges in the design process:</p> <div> <ul> <li>Finding optimal word lengths and fraction lengths</li> <li>Writing and understanding integer C-code is cumbersome and error prone</li> <li>Integer C code is hard to debug, pinpointing errors is difficult</li> <li>Translating (sequential) C to (parallel) HDL is a challenge</li> </ul> </div> <p>Simulink avoid these challenges by: 1. Seperating the data-types from the algoritms 2. Seperating the data-types from the value </p> <p>Simulink achieves this by providing the following capabilities:</p>⌨️ 快捷键说明
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