📄 t101_util.lst
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207 /****************************************************************************
208 * T10x Register No. and values for System and Tcon initial *
209 ****************************************************************************/
210 //====== InitT10x Register No. and values
211 REGADRVAL code stInitT10xP0[]={
212 //adr , value
213 //#if (defined T100A)|(defined T102)
214
215 #ifdef T100
0x0A , 0x60, //ADC_ROFF // Change by Sherman 06'01'10
0x0B , 0x60, //ADC_GOFF // Change by Sherman 06'01'10
0x0C , 0x60, //ADC_BOFF // Change by Sherman 06'01'10
0x1A , 0x87, //ADC_AGC_SEL_REG
0xCA , DODIV, //PLLDIV_O
0xC2 , 0x12, //POUT_VSYNC_CTRL_REG
//for image quality
0x6C , 0x80, //OP_SAT_REG
0x60 , 0x00, //DCTI_BW_REG
0x61 , 0x88,//For char clear //LUMA_PKCTRL_REG
0x62 , 0x18,//For char clear //BP_PKCOEF_REG
0x63 , 0x0F,//For char clear //HP_PKCOEF_REG
0x64 , 0x04,//For char clear //60 //LP_PKCOEF_REG
0x66 , 0x88,//For color clear enable DCTI //DCTI_GAINCO_REG
0X1C , 0xb0, //BLANK_SYNCLV_REG
#else
232 0x00 , 0x00,
233 0x01 , 0x00,
234 0x02 , 0x00,
235 0x0A , 0x80, // Change by Sherman for Gamma Adjustment 05'12'19
236 0x0B , 0x80, // Change by Sherman for Gamma Adjustment 05'12'19
237 0x0C , 0x80,
238 0x1a , 0xc7,
239 0xCA , DODIV,//0x10|DODIV, // Change by Sherman 06'01'18
240 0xc2 , 0x00,
C51 COMPILER V7.50 T101_UTIL 06/16/2006 15:29:43 PAGE 5
241 //for image quality
242 0x60 , 0x00,//01,
243 0x1c , 0xc0,
244 0x61 , 0x04,
245 0x62 , 0x0F,
246 0x63 , 0x0F,
247 0x64 , 0x04,
248 0x66 , 0x88,
249 #endif
250 0x97 , 0x95, //CSC_YCOEF_REG
251 0x98 , 0xCC, //CSC_CrRCOEF_REG
252 0x0D , 0x20, //5 //ADC_GENCTRL_REG
253 0xE0 , 0x92, //PW_MGRCTRL_REG
254 0x11 , 0x05, //YPbPr_CLPCTRL_REG
255 //Source Select--S Video
256 0x18 , 0x00, //ASRC_MUX_REG
257 0x19 , 0x07, //YCbCr_SW_REG
258 //Enable CSC
259 0x91 , 0x00, //BTIN_PATTERN_REG
260 //DSP Clock
261 #ifdef SEQ_MODE // For sequential mode, bruce, 2006/01/09
0xCB , (CPH1_PH | PHASE_DIV),
0xCC , (CPH3_PH | CPH2_PH),
0xC8 , DFDIV_S,
0xC9 , DIDIV_S,
0xCA , DODIV_S,
#else
268 0xC8 , DFDIV_40, //PLLDIV_F
269 0xC9 , DIDIV, //PLLDIV_I
270 #endif
271 //DSP Colck Polarity
272 0xC1 , 0xc8, //POUT_CTRL3_REG
273 //H&V Main Display Pixel Clock Setted
274 0xDC ,(H_Size&0xFF),//H Size //HMDISP_SIZE_L_REG
275 0xDD ,(H_Size>>8), //HMDISP_SIZE_H_REG
276 0xDE ,(V_Size&0xFF),//V Size //20 //VMDISP_SIZE_L_REG
277 0xDF ,(V_Size>>8), //VMDISP_SIZE_H_REG
278 //H&V Display Pixel Clock Setted
279
280 #ifdef _160_234
0xcb , 0x66,
0xcc , 0x42,
0x79 , 0x0d,
#endif
285 0xB0 , DISP_DFLT_HDENS, //H Start //DWHS_L_REG
286 0xB1 ,(DISP_DFLT_HDENS>>8), //DWHS_H_REG
287 0xB2 , DISP_DFLT_VDENS, //V Start //DWVS_L_REG
288 0xB3 ,(DISP_DFLT_VDENS>>8), //25 //DWVS_H_REG
289 0xB4 ,(H_Size&0xFF), //H Width //DWHSZ_L_REG
290 0xB5 ,(H_Size>>8), //DWHSZ_H_REG
291 0xB6 ,(V_Size&0xFF), //DWVSZ_L_REG
292 0xB7 ,(V_Size>>8), //DWVSZ_H_REG
293 0xB8 , DISP_DFLT_HTOTAL, //H Total //30 //PH_TOT_L_REG
294 0xB9 ,(DISP_DFLT_HTOTAL>>8), //PH_TOT_H_REG
295 0xBA , DISP_DFLT_VTOTAL, //V Total //PV_TOT_L_REG
296 0xBB ,(DISP_DFLT_VTOTAL>>8), //PV_TOT_H_REG
297 0xBC , DISP_DFLT_HSWIDTH, //HSYNC Width //PH_PW_L_REG
298 0xBD ,(DISP_DFLT_HSWIDTH>>8), //35 //PH_PW_H_REG
299 0xBE , DISP_DFLT_VSWIDTH, //VSYNC Width //PV_PW_L_REG
300 0xBF ,(DISP_DFLT_VSWIDTH>>8), //PV_PW_H_REG
301 //Scaling
302 0x72 , 0x33, //H Scale //SC_HOR_H1
C51 COMPILER V7.50 T101_UTIL 06/16/2006 15:29:43 PAGE 6
303 0x73 , 0x73, //SC_HOR_H2
304 0x74 , 0x00, //V Scale //40 //SC_VER_V1
305 0x75 , 0x40, //SC_VER_V2
306 //LineBuffer Prefill
307 0xe2 , 0x11,
308 0x84 , 0x00, //LINE_BUF_L_REG
309 0x85 , 0x10, //LINE_BUF_H_REG
310 0xE1 , 0xa0, //OPIN_CFG_REG
311 0x50 , 0x10, //45 //VSYNC_TIME_MEA_REG
312 0x38 , 0x50, //HSYNC_MISSCNT_L_REG
313 0x39 , 0x00, //HSYNC_MISSCNT_H_REG
314 0x3A , 0x20, //VSYNC_DLT_REG
315 0x3B , 0x03, //HSYNC_DLT_REG
316 #ifdef TCON
317 0xE0 , (0x91 | CPH1 | CPH2 |CPH3), //PW_MGRCTRL_REG, Bruce, 2006/01/09 for flexibility
318 #ifdef T100
0xE1 , 0xf4, //OPIN_CFG_REG
#else
321 0xe1 , 0xe0,
322 #ifdef _160_234
0xe0 , 0xbf,
#endif
325 #endif
326 #else
0xE0 , (0x91 | CPH1 | CPH2 |CPH3), //PW_MGRCTRL_REG
0xE1 , 0x00, //OPIN_CFG_REG
#endif
330 0x9C , 0x02, //DITHERING
331 0x90 , 0x04,//0x04, //IMG_FUNCTRL_REG
332 //De-Interlace enable
333 0x30 , 0x00,//(I1CReadByte(TW101, 0x30)|0x01)//DITLC_VSHDW_REG
334 #ifdef OUT_PIN_CONF
0xE1 , OUT_PIN_CONF, //OPIN_CFG_REG
#endif
337
338 #ifdef Enable_HelfSample
#ifdef T100A
0x79 , 0x20,
#else
0x78 , 0xa3,
#endif
#endif
345 #ifdef EnableDither
0x90 , ENCSC | ENDITHER,
0x9c , OutputBit,
#else
349 0x90 , ENCSC,
350 #endif
351 #ifdef T101A
0x90 , 0x07,
0x9c , 0x02,
#endif
355 #ifdef T112
356 0xea , 0x11,
357 #endif
358 0xff , 0x00// End of register settings, bruce, 2006/01/09
359
360 };
361
362 REGADRVAL code stInitT10xP2[]={
363 //adr , value
364 0x3f , 0x00, //ADC_ROFF // Change by Sherman 06'01'10
C51 COMPILER V7.50 T101_UTIL 06/16/2006 15:29:43 PAGE 7
365 0x24 , 0xe9, //0 //0x24
366 0x25 , 0x0F, //0x25
367 //Video Register Page Setted
368 0x2E , 0x82, //HACT_START_REG
369 0x2F , 0x30, //HACT_WIDTH_REG
370 0x3F , 0x00, //SOFT_RESET_REG
371 0xc0 , 0x14, //5 //0xc0
372 0xe0 , 0x10, //0xe0
373 0x0C , 0xcc,//8a, //CHROMA_AGC_REG
374 0x18 , 0x21, //CHROMA_DTO0_REG
375 0x19 , 0xf0, //CHROMA_DTO1_REG
376 0x1A , 0x7c, //10 //CHROMA_DTO2_REG
377 0x1B , 0x0f, //CHROMA_DTO3_REG
-
378 0x30 , 0x24, //VACT_START_REG
379 0x31 , 0x61, //VACT_HEIGHT_REG
380 0x82 , 0x42, //COMB_FILTERCFG_REG
381 #ifdef T100
-
0x04 , 0xD8, //15 //HAGC_REG // Change by Sherman for Gamma Adjustment 05'12'19
0x10 , 0x27, //AGC_PKNO_REG
0x00 , 0x00, //SRCSEL_COMBF_REG
0x03 , 0x00, //COMB_FILTERMODE_REG
0x02 , 0x4B, //YC_AGC_REG
0x11 , 0xb9, //20 //AGC_PKGT_CTRL_REG
#else
389 0x04 , 0xDD,//d8 // Change by Sherman for Gamma Adjustment 05'12'19
390 0x10 , 0x27,
391 0x02 , 0xcb,//4B,
392 0x11 , 0xb9,//FF,
393 #endif
394 //Color
395 0x01 , 0x00,//(I1CReadByte(TW101+4, 0x01)|0x01), //BW_CTRL_REG
396 #ifdef T100
0x80 , 0x05,//For char clear //LUMINANCE_PKCTRL_REG
0x07 , 0x01,//For color bar clear //YC_OPCTRL_REG
0x08 , 0x70, //CONTRAST_REG // Change by Sherman for G
-amma Adjustment 05'12'19
0x0A , 0x58, //25 //SAT_REG
0x09 , 0x18, //BRIGHT_REG
#else
403 0x08 , 0x70, // Change by Sherman for Gamma Adjustment 05'12'19
404 0x09 , 0x28,
405 0x80 , 0x05,
406 #endif
407 //0x2c , 0x30,
408 0x2d , 0x48,//60, // Add by Sherman 06'01'10s
409 0x3f , 0x01, //ADC_ROFF // Change by Sherman 06'01'10
410 0xff , 0x00, // End of register settings, bruce, 2006/01/09
411 };
412
413 static uCHAR cSVideo=0;
414 static uCHAR cYPbPr=0; // add by Sherman 06'01'12
415 /****************************************************************************
416 * Public Global Variable *
417 ****************************************************************************/
418 uDWORD m_dwTemp[2];
419 uWORD m_wDWHSZ=DWHSZ;
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