cordic16.vhd

CORDIC源码

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--  File: cordic16.vhd                                   --
--  created : July 09,2001 15:05                         --
--  mail to [e-mail]                          --
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library IEEE;
use IEEE.std_logic_1164.all;

entity cordic16 is
	port (
		clk        : in  STD_LOGIC;
		xi         : in  STD_LOGIC_VECTOR (15 downto 0);
		yi         : in  STD_LOGIC_VECTOR (15 downto 0);
		radius_out : out STD_LOGIC_VECTOR (19 downto 0);
		angle_out  : out STD_LOGIC_VECTOR (19 downto 0)
		);
end cordic16;

architecture cordic16 of cordic16 is 
	component pre is   
		port (                       
			clk    : in  std_logic;
			x_in   : in  STD_LOGIC_VECTOR (15 downto 0);
			y_in   : in  STD_LOGIC_VECTOR (15 downto 0);
			octant : out STD_LOGIC_VECTOR (2 downto 0);
			x_out  : out STD_LOGIC_VECTOR (15 downto 0);
			y_out  : out STD_LOGIC_VECTOR (15 downto 0)
			);
	end component pre;
	component core is 
		port (
			clk        : in  STD_LOGIC;
			x_in       : in  STD_LOGIC_VECTOR (15 downto 0);
			y_in       : in  STD_LOGIC_VECTOR (15 downto 0);
			octant_in  : in  STD_LOGIC_VECTOR (2 downto 0);
			octant_out : out STD_LOGIC_VECTOR (2 downto 0);
			radius     : out STD_LOGIC_VECTOR (19 downto 0);
			angle      : out STD_LOGIC_VECTOR (18 downto 0)
			);
	end component core;
	component post_20b15i is
		port (
			clk           : in  STD_LOGIC;
			scaled_radius : in  STD_LOGIC_VECTOR (19 downto 0);
			input_angle   : in  STD_LOGIC_VECTOR (18 downto 0);
			octant        : in  STD_LOGIC_VECTOR (2 downto 0);
			angle         : out STD_LOGIC_VECTOR (19 downto 0);
			radius        : out STD_LOGIC_VECTOR (19 downto 0)
			);
	end component post_20b15i;
	signal	radius :  STD_LOGIC_VECTOR (19 downto 0);
	signal	angle  :  STD_LOGIC_VECTOR (19 downto 0);
	
	signal x : STD_LOGIC_VECTOR (15 downto 0);
	signal y : STD_LOGIC_VECTOR (15 downto 0);

	signal x_to_core   : std_logic_vector (15 downto 0);
	signal y_to_core   : std_logic_vector (15 downto 0);
	signal oct_to_core : std_logic_vector (2 downto 0);
	
	signal scaled_radius : std_logic_vector (19 downto 0);
	signal z_to_post     : std_logic_vector (18 downto 0);
	signal oct_to_post   : std_logic_vector (2 downto 0);
	
begin
	
	preprocessing : pre
	port map (
		clk    => clk,
		x_in   => x,
		y_in   => y,
		octant => oct_to_core,
		x_out  => x_to_core,
		y_out  => y_to_core
		);

	processing : core
	port map (
		clk        => clk,
		x_in       => x_to_core,
		y_in       => y_to_core,
		octant_in  => oct_to_core,
		octant_out => oct_to_post,
		radius     => scaled_radius,
		angle      => z_to_post
		);

	postprocessing : post_20b15i
	port map(
		clk           => clk,	
		scaled_radius => scaled_radius,
		input_angle   => z_to_post,
		octant        => oct_to_post,
		angle         => angle,
		radius        => radius
		);

	process(clk)   
	begin
		if clk'event and clk='1' 
                   then

		    x <= xi;     -----input reg
                    y <= yi;     -----input reg

                    radius_out <= radius;    -----output reg
                    angle_out  <= angle;     -----output reg	

		end if;		
	end process;			
		
end cordic16;