📄 at76c502.h
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/**************************************************************************//* */ /* Copyright (c) 1999-2000 by Atmel Corporation */ /* */ /* This software is copyrighted by and is the sole property of Atmel */ /* Corporation. All rights, title, ownership, or other interests */ /* in the software remain the property of Atmel Corporation. This */ /* software may only be used in accordance with the corresponding */ /* license agreement. Any un-authorized use, duplication, transmission, */ /* distribution, or disclosure of this software is expressly forbidden. */ /* *//* This Copyright notice may not be removed or modified without prior */ /* written consent of Atmel Corporation. */ /* */ /* Atmel Corporation, Inc. reserves the right to modify this software */ /* without notice. */ /* */ /* Atmel Corporation. *//* 2325 Orchard Parkway literature@atmel.com *//* San Jose, CA 95131 http://www.atmel.com *//* *//**************************************************************************//**************************************************************************//**************************************************************************//** */ /** FastVNET (PCMCIA) NDIS Miniport Driver */ /** *//** AT76C502 Related definitions *//** *//**************************************************************************//**************************************************************************/#ifndef __at76c502_h_OK__#define __at76c502_h_OK__//// FastVNet registers currently used//#define GCR 0x00 // (SIR0) General Configuration Register (GCR)#define BSR 0x02 // (SIR1) Bank Switching Select Register (BSR)#define AR 0x04#define DR 0x08#define MR1 0x12 // Mirror Register 1 #define MR2 0x14 // Mirror Register 2 #define MR3 0x16 // Mirror Register 3 #define MR4 0x18 // Mirror Register 4 #define GPR1 0x0c#define GPR2 0x0e#define GPR3 0x10//// Constants for the GCR register.//#define GCR_REMAP 0x0400 // Remap internal SRAM to 0#define GCR_SWRES 0x0080 // BIU reset (ARM and PAI are NOT reset) #define GCR_CORES 0x0060 // Core Reset (ARM and PAI are reset)#define GCR_ENINT 0x0002 // Enable Interrupts #define GCR_ACKINT 0x0008 // Acknowledge Interrupts#define BSS_SRAM 0x0200 // AMBA module selection --> SRAM#define BSS_IRAM 0x0100 // AMBA module selection --> IRAM//// Constants for the MR registers.//#define MAC_INIT_COMPLETE 0x0001 // MAC init has been completed#define MAC_BOOT_COMPLETE 0x0010 // MAC boot has been completed#define MAC_INIT_OK 0x0002 // MAC boot has been completed#endif
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